3D IC Technology Forum

Thursday, October 1^st, 2009 〡08:30 –17:30
Room 201ABC, 2F, Taipei International Convention Center, Taipei
Event Fee : Free (Pre-registration is required)

Theme: The Next Trillion

Forum Chair: Dr. Ho-Ming Tong, Chairman, SEMI Taiwan PKG&TEST Committee / GM & CTO, ASE Group
Morning Session Chair: Mr. Rutgers Chow, Member, SEMI Taiwan IC Committee / VP, Operation, AVIZA Technology
Afternoon Session Chair: Mr. Walter Jau, Director, Corporate R&D / Corporate Engineering, ASE Group
Moderator: Dr. Ho-Ming Tong, Chairman, SEMI Taiwan PKG&TEST Committee / GM & CTO, ASE Group

Outline:
Due to rapid advancement of packaging technology and stronger demand on System in Package, electronic system developers now consider semiconductors as integrated system rather than separated components. Therefore, they need to work closely with packaging houses to obtain timely information to aide in their design decisions for cost and time-to-market requirements. The days for IC and package to be considered independently are also numbered. Take through silicon via, for instance, IC-package-system co-design is needed to reap the full benefits of these 3D SiP technologies, and to achieve functional diversity, reduce form factor, higher performance as well as heterogeneous integration.

The Taiwan semiconductor cluster has already proven its ability to create a highly successful “Taiwan Experience” for the current 2D IC industry and market. The time has arrived for us to target and transfer this new paradigm to 3D IC realm, starting from Taiwan semiconductor infrastructure’s core value to enablement of global semiconductor supply chain.

This SEMICON Taiwan 2009 3D IC Technology Forum will invite professional perspectives from industry experts, product application drivers, and potential technology solution providers to address the above key issues, with special attention to 3D IC solution design validation and Taiwan semiconductor value chain synergy.

Agenda:

08:30 – 09:00	Registration
09:00 – 09:10	Opening Remarks Mr. Terry Tsao, President, SEMI Taiwan & Southeast
09:10 – 09:50	Keynote Speech - Industry Overview Dr. Ho-Ming Tong, Chairman, SEMI Taiwan PKG&TEST Committee / GM & CTO, ASE Group
09:50 –10:30	Keynote Speech - 3D IC Market Outlook Mr. Mark Stromberg, Principal Research Analyst, Gartner ● Global 3D IC Market Trend ● Emerging Opportunities Across the Semiconductor Food Chain
10:30 –10:40	Break Time
10:40 –11:20	Keynote Speech - Taiwan 3D IC Value Chain: The Next Revolution for Taiwan Semiconductor Industries Dr. YJ Chan, VP & General Director, Electronics and Optoelectronics Research Labs, ITRI ● Past, Now and Future ● Taiwan Supply Chain’s Opportunity & Value-Added
11:20 –12:00	Invited Presentation - Technology Challenges - From IC to System Dr. Michael J. Shapiro, Chief Technologist 3D Development, STSM, Systems and Technology Group, IBM
12:00 –13:00	Lunch Break
13:00 –13:40	Technology Solutions – Design Mr. KC Wu, Associate Vice President, Faraday Technology Corporation ● Design trend & challenge ● Current solution in SiP design ● Future challenge in 3D package ● Opportunity for Taiwan infrastructure
13:40 –14:20	Test Strategy & Challenge for 3D IC Dr. Erik Volkerink, Chief Scientist, Verigy Ltd. 1. Highlight various 3D related trends ● Integration trends ● Performance trends ● Application trends 2. Examine various challenges ● Design tools ● Thermal issues ● Cross-talk issues ● Manufacturing yield and test issues 3. Focus on various test cell related challenges, solutions, and opportunities
14:20 –15:00	3D IC Metrology and Inspection Challenges Mr. Irfan Malik, Program Director, KLA-Tencor Corp. ● Deep Silicon Etch depth / quality measurement ● TSV stop on metal measurement ● TSV isolation quality measurement ● Double side pattern alignment
15:00 –15:10	Break Time
15:10 –15:50	Low Temperature, High Reliability TSV Processing Mr. Kevin Crofton, Senior VP and GM, PVD, Etch and CVD Business Units, AVIZA 1. 3D-IC TSV: range of needs depending on via first, middle or last ● High Density & high AR for via first ● Low Temperature for via middle and last ● Handling Thin Wafer on carriers 2. Process Requirements & solution alternatives (overview with focus on your core competency) 3. Benchmark & Characterizations(focus on your core competency)
15:50 –16:30	CVD Material Requirements for High AR TSV Dr. Kazutaka Yanagita, Senior Scientist, Air Liquide
16:30 –17:30	Panel Discussion: Challenges vs. Solutions - From IC to Systems Moderator: Dr. Ho-Ming Tong, Chairman, SEMI Taiwan PKG&TEST Committee / GM & CTO, ASE Group Panelists: 1. Mr. Mark Stromberg, Principal Research Analyst, Gartner r 2. Dr. YJ Chan, VP & General Director, Electronics and Optoelectronics Research Labs, ITRI 3. Mr. KC Wu, Associate Vice President, Faraday Technology Corporation 4. Dr. Erik Volkerink, Chief Scientist, Verigy Ltd. 5. Mr. Irfan Malik, Program Director, KLA-Tencor Corp. 6. Mr. Kevin Crofton, Senior VP and GM, PVD, Etch and CVD Business 7. Dr. Kazutaka Yanagita, Senior Scientist, Air Liquide
17:30	Adjournment

>> Programs are subject to change without prior notice.
>> All presentations will be conducted in English.

Organized by
Sponsored by

Forum Chair Introduction:

● General Manager of Group R&D, ASE Group ● IEEE Fellow for leadership in leading-edge integrated circuits technology ● Electronics Manufacturing Technology Award from IEEE Components ● 2005 the highest recognition for technical leaders ● He has authored/co-authored 112 patents, 100+ technical publications, as well as 2 books and 2 special journal issues on electronic packaging. Top

Morning Session Chair Introduction:

Mr. Rutgers Chow, Member, SEMI Taiwan IC Committee / VP, Operation, AVIZA Technology Mr. Chow has over 20 years of electronics and semiconductor equipment industry experience. Since 1990, he has held multiple positions in sales, operations and engineering. Prior to joining Aviza, he served as regional vice president for Taiwan, China, and Southeast Asia at Shipley Co. (now Rohm and Haas Electronics Materials). During a stint at Novellus Systems, Mr. Chow was director of sales, where he was chartered with growing the company’s business in Taiwan, China and Southeast Asia. In addition, he spent 10 years at Tegal, where he held a variety of positions with increasing responsibility in R&D, field process development as well as demo lab manager for Tegal’s Japan operations and general manager of the Company’s Asia operations. Prior to working in the semiconductor equipment arena, Mr. Chow was a process engineer at Northern Telecom in San Diego. Mr. Chow holds a bachelor of science degree in chemistry from the University of Michigan and a master of science degree in chemical engineering from the University of Virginia. Top

Afternoon Session Chair Introduction:

Mr. Walter Jau, Director, Corporate R&D/Corporate Engineering, ASE Group ● Executive Secretary Semi TW Package & Test Committee ● Ph.D. Candidate, N.C.K.U. ● R&D Manager, ASE Material ● Project Manager, ASE-KH ● Owned 31+ patents Top

Moderator Introduction:

Dr. Ho-Ming Tong, Chairman, SEMI Taiwan PKG&TEST Committee / GM & CTO, ASE Group ● General Manager of Group R&D, ASE Group ● IEEE Fellow for leadership in leading-edge integrated circuits technology ● Electronics Manufacturing Technology Award from IEEE Components ● 2005 the highest recognition for technical leaders ● He has authored/co-authored 112 patents, 100+ technical publications, as well as 2 books and 2 special journal issues on electronic packaging. Top

Speaker Introduction

	Dr. Ho-Ming Tong, Chairman of SEMI Taiwan PKG&TEST Committee / GM&CTO, ASE Group ● General Manager of Group R&D, ASE Group ● IEEE Fellow for leadership in leading-edge integrated circuits technology ● Electronics Manufacturing Technology Award from IEEE Components ● 2005 the highest recognition for technical leaders ● He has authored/co-authored 112 patents, 100+ technical publications, as well as 2 books and 2 special journal issues on electronic packaging. Top
	Mr. Mark Stromberg, Principal Research Analyst, Gartner ● Packaging, Assembly, Test Equipment and SATS Industry Analyst 2000 Present ● Design Automation Software Analyst 1999-2000 (Sectorbase.com) ● E-Business Software/Hardware Market Consultant (Gartner) ● Semiconductor Equipment Analyst 1996-1998 (VLSI Research) ● BS Economics, San Jose State University, 1995 Top
	Dr. YJ Chan, VP & General Director, Electronics and Optoelectronics Research Labs, ITRI ● Deputy General Director, EOL/ITRI ● Professor, National Central University ● Professor, National Chiao Tung University ● Chairman of EE Dept., National Central University ● Received Science Paper Award of Far Eastern Y. Z. Hsu Science and Technology Memorial Foundation in 2006 ● Owned 18 patents Top
	Dr. Michael J. Shapiro, Chief Technologist 3D Development, STSM, Systems and Technology Group, IBM ● B.S., Virginia Tech M.S. and Ph.D., Georgia Tech ● 2010 General Chair of the IEEE International Interconnect Technology Conference ● IBM Master Inventor ● IBM Corporate Patent Award for fluorosilicate glass (FSG) which is now used industry-wide in semiconductor device wiring levels. Top
	Mr. KC Wu, Associate Vice President, Faraday Technology Corporation ● Associate Vice Precedent, Faraday Technology Corp. ● Chairman of SNUG Taiwan, 2008 & 2009 Technical Committee ● Director of Design Development, Faraday Technology Corp. ● Design Engineer of CCL, ITRI ● MS from National Chiao Tung University, Hsinchu ● Owned 15 patents Top
	Dr. Erik Volkerink, Chief Scientist, Verigy Ltd. ● Dr. Volkerink manages Verigy Labs and serves as Chief Scientist of Verigy. In this role, he is responsible for managing university relations, long-term research, technical trend scanning, as well as managing Verigy’s patent portfolio. ● Dr. Volkerink also serves as a Consulting Assistant Professor in the Electrical Engineering Department of Stanford University and as Assistant Director of Stanford’s Center for Reliable Computing. ● Dr. Volkerink research area is Semiconductor Design & Test. He is recipient of the Best Paper Award at the CPA conference as well as a Best Paper Award Nomination of the Design Automation Conference (DAC). ● He is the Corporate Track Chair of the International Test Conference (ITC), Cost-of-Test Section Lead of the International Technology Roadmap for Semiconductors (ITRS) ● He is Registration Chair of the Pacific Northwest Test Workshop. ● He was also a Keynote Speaker of the Future of ATE Workshop (FATE) at ITC as well as Session Chair at various conferences. ● Previously, he worked with Hewlett-Packard Company, Agilent Technologies, and various companies in the Netherlands. Top
	Mr. Irfan Malik, KLA-Tencor ● MS Chemical Engineering, University Of Missouri – Rolla ● Author of more than 25 papers and presentations Top
	Mr. Kevin Crofton, Senior VP and GM, PVD, Etch and CVD Business Units, AVIZA ● 16+ years of experience in the industry ● Sr. VP of Customer Ops, NEXX Systems ● VP & GM Adv. Packaging & Automation Division, Newport Corp. ● MD & GM CMP/ Clean Products, Lam Research Corp. ● Bachelor’s degree in Aerospace Engineering, Virginia Tech & Masters Degree inInt’l. Business, American University ● Keynote speaker: Semi Taiwan ‘08, Photonics & Microelectronics Forum, Boston MA – Feb ‘03 ● Articles – Semi, Semi Int’l & Microelectronics Top
	Dr. Kazutaka Yanagita, Senior Scientist, Air Liquide ● International Expert, Air Liquide ● Has worked in the gas/chemical industry for 11 years, serving in evaluating CVD/ALD processes, precursors and its delivery, and trace impurity analyses. ● Ph. D. degree in chemistry from Tohoku University in Japan. Top