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Imagine your Digital and Energy Transition with Leti - Day1

 Date:

 Wednesday, September 13th, 2017

 Time: 

 11:00 - 17:00

 Venue:

 Room 449, Taipei Nangang Exhibition Center, Hall 1, Taipei, Taiwan

 Theme:

  Imagine your Digital and Energy Transition with Leti

 

 

 Forum Outline: 

 
Leti is a technology research institute localized in Grenoble (France) and recognized as a global leader in miniaturization technologies enabling smart, energy-efficient and secure solutions. Committed to innovation, its teams create differentiating solutions for Leti’s industrial partners. By pioneering new technologies, Leti enables innovative applicative solutions that ensure competitiveness in a wide range of markets. Leti tackles critical, current global issues such as the future of industry, clean and safe energies, health and wellness, safety & security…
 
Leti's multidisciplinary teams deliver solid micro and nano technologies expertise, leveraging world-class pre-industrialization facilities. For 50 years, the institute has been building long-term relationships with its industrial partners providing tailor-made solutions and a clear intellectual property policy.
 
A team of experts will be present during SEMICON Taiwan 2017 in order to present Leti's activities and discuss potential collaborations:
-       Silicon Platform for micro and nano technologies including advanced lithography innovations such as multi-ebeam lithography and  Nanoinprint
-       Digital, RF and advanced 3D technologies to sustain 5G and IoT systems roadmaps
-       Imaging and Photonics technologies including MicroLed displays and sensors
 

 

Organizer:

 

 

 

Co-organizer:

  

 

 

Sponsor:

         
 

 

 

 

 

 

 

Agenda

Time

Topic & Speaker

11:00 - 12:00

 Microelectronics activities at CEA-Leti

 Technologies portfolio & roadmaps

 1- Digital

 2- Memory

 3- 3D

 Resources & Platforms

 Fabrice Geiger, Head of Silicon Technologies Division

 Carlo Reita, Director of Technical Marketing and Strategy, Nanoelectronics, in the CTO Office

 Hughes Metras, Director of Nanoelec IRT 3D Technologies

 Abstract:

CEA-Leti, the Laboratory for Electronics and Information Technologies, mainly aims at helping companies to increase their competitiveness through technological innovation and transfer of technical know-how to industry. This laboratory has been involved in electronics research for over 30 years. The MOS 200/300 platform provides 200mm and 300mm CMOS wafer processing, which can be applied to both semiconductor and microsystem devices. The MEMS200 platform produces Micro-Electro Mechanical Systems (MEMS). Together, the two programs have 6,500m² of clean room space, 500 process tools and a combined staff of more than 900 people.

This session will present microelectronics activities at CEA-Leti are using this technological research platform to cover research topics in a wide range of applications:

  • CMOS Process development for digital and RF: Expertise in new material integration in CMOS processes (like high k material considered in this project), capability to test a new equipment in its clean rooms, expertise in simulation, modelling and characterization, 3D process integration and  more than 20 years expertise on Silicon-On-Insulator (from SOI substrate to SOI devices modelling, characterization and design, CEA-Leti is working very close with SOITEC, with a common R&D lab)

  • CMOS memories, enabling to our customers a screening of advanced materials for new advanced memories like split gate memories or  different resistive RAMs (as phase-change memories, conductive-bridge memories and oxide-resistive memories)  as well as advanced characterization and simulation of NVM cells

  • MEMS & NEMS: Mechanical sensors and actuators (accelerometer, gyro-meter, pressure sensor, force sensor, RF switch), Optical MEMS (adaptive optical actuators, micro-scanner, optical switch), Magnetic MEMS (micro-fluxgate, inductive head sensor, magnetic switch)

  • New High Power devices: expertise from material epitaxy on Silicon (GaN/Si) to devices implementation and characterization for future high power systems in electrical cars

13:30

 CEA-Leti General Presentation

 Michael Tchagaspanian, VP Sales & Marketing

16:00 - 17:00

 FDSOI Technology & Design Support

 Fabien Clermidy, Head of the Wireless Communication Department

 Carlo Reita, Director of Technical Marketing and Strategy, Nanoelectronics, in the CTO Office

 Ali Erdengiz, SoC Design Business Developper, Circuit Architecture & Embedded Software

 Abstract:

Fully-Depleted-Silicon-On-Insulator (FDSOI)  is a microelectronic digital technology platform issued from the early works done by CEA-Leti in the early 90’s. Jointly developed as a manufacturing platform between CEA-Leti and ST Microelectronics in the 2000’s, the technology has been transferred to silicon foundries as Samsung and Globalfoundries to become today a major alternative of FinFet for IoT, Ultra Low Power pervasive computing, smart driving, mixed signal, and RF. Pioneer of the Silicon-On-Insulator research, CEA-Leti is at the heart of the ecosystem which developed all the ingredients required to benefit from SOI up to product level. After more than 20 years of development, CEA-Leti is ideally positioned to provide an accurate and reliable vision of how FDSOI technology works and which benefits can be obtained through its application.

This session dedicated to FDSOI will consist of very short introductive presentations given by technical experts from CEA-Leti:

  • Focus is made on FDSOI technology and device behavior, process integration route is presented, and electrical device performances are presented and benchmarked against other types of transistors. Then Leti-UTSOI models, the most complete FDSOI transistor models developed by CEA-Leti, are presented.

  • Then an extended FDSOI design presentation will follow, with the objective to show by example how to take full advantage of the technology properties when applying to complex circuit design. Topics discussed will span from LVT/RVT and Poly-Biasing (PB) co-integration to specific design solutions for efficiently using back-biasing, for Ultra-Wide-Voltage-Range (UWVR) and Ultra-Low-Power (ULP) applications with voltages down to 400mV.

 

 Adjournment

■ Programs are subject to change without prior notice. 

■ All presentations will be conducted in English. 

■ No recording/photography during the seminar.

 

Price

Early Bird / SEMI Member

Original Price (Aug 16 - Onsite)

Free

Free

(Currency: NTD)

 


Contact

Mr. Louis Didier

Email: didier.louis@cea.fr 

 

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