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ITC-Asia Day 3

Date:

 Friday, September 15, 2017

 

Time:

09:00 - 16:40 

Venue

504abc, Taipei Nangang Exhibition Center, Hall 1

Theme:

 

 

 Forum Chairman:

 

 

 Forum Moderator:

 

 

 Forum Outline: 

 

 

 

Organizer:

 

 

 

 

 

Co-Organizer:

 

 

 

 

 

Sponsor:

               

議程表

Agenda

Time

Speaker / Topic

09:00 - 10:30

 Keynote Session (II)

  Seven Major Trends that are Changing how we Test ICs

 Phil Nigh, Global Foundries

 

 Test Emerging Memories

 Robert Aitken, ARM Research

10:30 - 10:50

 Coffee Break

10:50 - 12:05

 EDA Session

  The Emerging Applications of Machine Learning in Testing

 Yu Huang, Mentor, A Siemens Business

 

 Test for InFO and SoC Session

 Fan-Out Wafer Level Chip Scale Package Testing

 Hao Chen, Hung-Chih Lin, and Min-Jer Wang

 Testing-for-Manufacturing (TFM) for Ultra-thin IPD on InFO

 Tang-Jung Chiu

 Test Strategy for Storage SoCs

 Abhishek Bhattacharya and Ramesh Tekumalla

 

 Memory Test Session

 Adaptive Block-Based Refresh Techniques for Mitigation of Data Retention Faults and Reduction of Refresh Power

 Shyue-Kung Lu

  Software-Hardware-Cooperated Built-In Self-Test Scheme for Channel-Based DRAMs

 Tsung-Fu Hsien, Jin-Fu Li, Kuan-Te Wu, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, and Yung-Fa Chou

  Adapting an Industrial Memory BIST solution for testing CAMs

 Jais Abraham, Uttam Garg, Glenn Colon-Bonet, Ramesh Sharma, Chennian Di, Benoit Nadeau-Dostie, Etienne Racine, and Martin Keim

 

12:05 -13:30

 Lunch Break

13:30 - 14:45

 Fabless and IDM Session

  DFT Challenges and Solutions for Automotive ICs

Ying-Yen Chen, RealTek Semiconductor Corp, Taiwan

 Multi-Pronged Strategy to Reduce Scan Test Cost at Advanced Process Nodes

 Jianguo Ren, MediaTek Inc., Taiwan

 What Do We Make the System Reliable?

 Xinli Gu, Huawei Technologies, USA

 

 On-Chip Test Infrastructure Session

 Reconfigurable Access to On-Chip Infrastructure

 Michael Kochte, Rafal Baranowski, and Hans-Joachim Wunderlich

 On the Effects of Real-Time and Continuous Measurement with a Digital Temperature and Voltage Sensor

 Yousuke Miyake, Yasuo Sato, and Seiji Kajihara

  Enhancing Security of Logic Encryption Using Embedded Key Generation Unit

 Rajit Karmakar, Santanu Chattopadhyay, and Rohit Kapur

 

 Advanced Test Practices Session

  A Mathematical Model to Assess the Influence of Parallelism in a Semiconductor Back-End Test Floor

 Davide Appello, Mariapina Laurino, and Marco Pranzo

  A Fully Automatic Test System for Characterizing Large-Array Fine-Pitch Micro-Bump Probe Cards

 Erik Jan Marinissen, Ferenc Fodor, Bart De Wachter, Joerg Kiesewetter, Eric Hill, and Ken Smith

  Test Item Priority Estimation for High Parallel Test Efficiency under ATE Debug Time Constraints

 Young-Woo Lee, Inhyuk Choi, Kang-Hoon Oh, James Jinsoo Ko, and Sungho Kang

 

14:45 - 15:00

 Coffee Break

15:00 – 16:40

 OSAT Session

 The Challenge to Increase Fault Coverage in IC Testing Process

 Herbert Tsai, Chroma ATE Inc., Taiwan

  A Probe Card Metrology Process Enabling Fast Feedback Loops to Reduce Operational and Maintenance Related cost

 Martin Kunz, NanoFocus, Germany

 

 Verification and Fault Tolerance Session

 Speeding up Power Verification by Merging Equivalent Power Domains in RTL Design with UPF

 Charles C.-H. Hsu and Charles H.-P. Wen

 Assignment for Fault Tolerant Stochastic Computing with Linear Finite State Machines

 Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki and Tomoo Inoue

 An Integrated Design Environment of Fault Tolerant Processors with Flexible HW/SW Solutions for Versatile Performance/Cost/Coverage Tradeoffs

 Yi-Ju Ke, Yi-Chieh Chen and Ing-Jer Huang

 

 Embedded Tutorials

  At-Speed Test Challenges for Giga-Size and Giga-Hertz Designs

 Kun-Han (Hans) Tsai, Mentor, A Siemens Business, USA

  Deep Neural Network Design and Applications on Testing

 Jin-Fu Li, National Central Univ., Taiwan

  Statistical Soft Error Rate (SSER) for Nanometer Designs

 Charles Wen, National Chiao-Tung Univ., Taiwan

 

 

■ Programs are subject to change without prior notice. 

■ All presentations will be conducted in English. 

■ No recording/photography during the seminar.

 

Price

SEMI Member

Original Price

       

     

 


Contact

SEMI Taiwan

Ms Grace Wang

TEL: 886.3.560.1777 EXT. 503

Email: gwang@semi.org 

 

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