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SiP Global Summit 3D IC TEST Forum |
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For online registeration, please click "Register Now"! |
Wednesday, September 7, 2011
13:00 –17:20
Room 201ABC, 2F, TICC
Event Fee : Free (Pre-registration is required)
Theme :
Test Challenges and Solution in the New Era of Heterogeneous Integration
Chair & Moderator:
Mr. Mike Liang, Chairman of SEMI Taiwan Testing Committee / President & CEO, KYEC
Co-chairs :
1. Mr. Roger Hwang, Director, ASE Group
2. Dr. Mike Ma, Vice President, Corporate R&D, SPIL
3. Mr. Sam Tsai, Sr. Director, Spirox
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Sponsored by |
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Technical Sponsored by
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Outline :
3D-IC technologies are now on the leading edge of innovation. It can be Heterogeneous IP
cores from different suppliers can be integrated in one single package. However, multiple
Packaging and Testing challenges must first be involved to meet the proper production yield
rate to make it from concept to commercialization.
The increasing 3D-IC increased design and mechanical package complexity of 3D-IC will
lead to increase a significant manufacturing test challenge.
It is crucial for the entire supply chain partners from material suppliers, design houses, test
equipment suppliers, package and testing houses to get together to come out cost effective
test mythologies and strategies to make this innovation to commercialization as soon as
possible.
Taiwan 3D-IC test forum had invited world class leading experts from design and testing
houses, equipment suppliers and end users to share their multiple views of testing solutions.
See you at SEMICON Taiwan on Sep. 8th 2011.
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13:00 – 13:30 |
Registration |
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13:30 – 13:40 |
Welcome Remarks 1.Mr. Jonathan Davis, Global Semiconductor Business Executive Vice President, SEMI 2. Mike Liang, President & CEO, KYEC |
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13:40 – 14:20 |
Amer Cassier, Sr. Staff Product Development Engineer, Qualcomm |
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14:20 – 15:00 |
Challenges and Solutions for Testing of TSV and MicroBump Devices Benjamin N. Eldridge, Senior VP, R&D and CTO, FormFactor Inc. |
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15:00 – 15:40 |
3D IC Testing Strategies and Experiences Greg Smith, General Manager, Computing and Communications Business Unit, Semiconductor Test Division. Teradyne |
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15:40 – 16:00 |
Break |
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16:00 – 16:40 |
3D IC Test Challenges from Assembly Process Perspective Calvin Cheung, VP, Engineering and Technical Promotion, ASE |
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16:40 – 17:20 |
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17:20 |
Adjournment |
● Programs are subject to change without prior notice.
● All presentations will be conducted in English.
Chair's Introduction:
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Mr. Mike Liang, Chairman of SEMI Taiwan Testing Committee / President & CEO, KYEC
● President & CEO, King Yuen Electronics Co. ,Ltd.
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Co-Chairs' Introduction:
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Mr. Roger Hwang, Director, ASE Group
● Education: ME, National Cheng Kung University, Electrical Engineering
● Experience: Product Test Engineer/ASE TEST, Customer Technical Support Manager/ASE TEST
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Dr. Mike Ma, Vice President, Corporate R&D, SPIL
● Professional Experience ▲Siliconware Precision Industries Co., Ltd. (SPIL), Taiwan (2010~Present) −Vice President: Corporate Research and Development ▲United Microelectronics Corporation (UMC), Taiwan
2000~2010 −Division Director: Corporate Marketing −Division Director, Exploratory Technologies-Advanced Technology Development (ATD): accountable for 28nm platform (SiON and HK&MG) and 65nm Silicon-On-Insulator (SOI) technology development; managing external research programs (SEMATECH-FEP/Litho/3DIC, and performed assessments of emerging technologies) −Deputy Division Director, Logic Development- ATD: technology project manager for 90nm/ 65nm, performed technical marketing; interfaced with IC design community for design kits delivery and DFM strategy setting −Department Director, Process Engineering- Integration, Fab 8DWafertech LLC (now “A TSMC Company”), Camas, WA, USA
1998~2000 −Deputy Department Manager, Technology Development department −Section Manager, Process Engineering II department ▲Institute of Microelectronics (IME), Singapore 1997~1998 −Member of Technical Staff in Deep Sub-micron IC (DSIC) program ▲United Microelectronics Corporation (UMC) group, Hsinchu, Taiwan
1993~1997 −Section Manager; start-up team and Diffusion Process section, in the spun-off United Semiconductor Corporation (USC, now UMC’s Fab 8B) −Principal Engineer, start-up team and Diffusion/Implant Process, Fab 8A −Senior Engineer, Diffusion/Film process, Fab IC1 (4” fab) ▲Metals Industry R&D Center (MIRDC), Kaohsiung, Taiwan
1991~1993 ● Education −Ph. D. / Material Science and Engineering; North Carolina State University, Raleigh, NC, USA (1992) −M. S. / Materials Engineering; Northeastern University, Boston, MA, USA(1986) −B. S. / Metallurgy &Material Engr; National Cheng-Kung University, Taiwan (1982)
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Mr. Sam Tsai, Sr. Director, Spirox
● Education: BSME, National Cheng-Kung University MSME, Texas Tech University MSEE, Colorado State University Complete PhD EE Courses of Colorado State University
● Experience: 23 years in R&D of HP/Agilent in Colorado, USA 《Top》
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Welcome Remarks Speaker Introduction:
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Mr. Jonathan Davis, President, Global Semiconductor Business
Jonathan Davis is a member of the Global Executive Team of SEMI, the global industry association serving 2,000 member companies that provide equipment, materials and services used to manufacture semiconductors, displays, nano-scaled structures, micro-electromechanical systems (MEMS) and related technologies.
Since September 2007, he serves as Executive Vice President with oversight responsibility for the association's global exposition operations, corporate marketing, creative services, communications and public relations, information products and publishing functions as well as the acclaimed SEMI Industry Research and Statistics operations and Environmental Health and Safety Department.
Prior to his current position, Davis was in charge of Global Marketing and Communications, having advanced over a prior decade through the positions of manager, director, senior director and vice president with marketing, communications and public relations duties.
Before holding positions in marketing, communications and PR, Davis managed the SEMI Membership Department. Davis joined SEMI in 1992 to initiate the organization's Outreach Program, through which he conducted and reported on SEMI member company visits throughout North America and informed management about customer requirements and satisfaction.
Before joining SEMI, Davis worked for nine years at HNTB, a national architecture and engineering firm. He earned a 5-year architecture degree from the Kansas State University College of Architecture and Design and studied at the University of Missouri at Columbia School of Journalism. Davis is a member of the American Society of Association Executives and the Public Relations Society of America.
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Speakers' Introduction:
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Mr. Amer Cassier, Sr. Staff Product Development Engineer, Qualcomm
● Supporting the development next generation tech. and its transfer to high volume manufacturing : High performance, low power caches for mobile processors, Non-Volatile memories, and 3D TSV. ● Received MSEE from University of Southern California in 2006 ● Joined Qualcomm Product Development Team in Aug 2001 ● Received BSEE from University of Colorado Boulder in May 2001 ● Co-authored paper on Dual Core Oxide, high performance, low power, Multi Vt, 8 transistor SRAM Cell for Mobile SOC Applications. (2010 Symposium on VLSI Technology) ● Co-authors : Hoang Nguyen (Sr. Staff Eng) ● Sam Gu ( Sr. Staff Eng)
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Mr. Benjamin N. Eldridge, Senior VP, R&D and CTO, FormFactor Inc.
●FormFactor Inc 1994-2011 ●IBM Research Division, 1984-1994 ●MS Physics RPI 1984 ●BSEE Union College 1982 ●186 Issued US and Foreign Patents.
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Mr. Sam Ko, Deputy Director, KYEC
● Speaker, ITC 2009. National Chiao Tung University of SOC and RF testing.
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Presentation Abstract:
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Amer Cassier, Sr. Staff Product Development Engineer, Qualcomm
Semiconductor industry has adopted several interconnect technologies to meet system functionality, scaling, performance and value requirements by integrating multiple chips into single module like MCP, stacked IC package, PIP, SIP, 3D SIP, POP, etc…. However, meeting the requirements of next generation mobile systems with existing technology will be challenging. As a result, the industry has been collaborating on the development of a new interconnect technology, Through Silicon Via (TSV), to meet emerging requirements. TSV offers many advantages for next generation, low power, mobile systems such as density, functionality, performance, power savings, and form factor scaling. On the other hand, this technology presents the industry with a wide range of implementation challenges. This paper will highlight options and alternatives to address key challenges related to engineering verification, diagnosis, and manufacturing test flow for wide IO Memory on Mobile SOC.
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Challenges and Solutions for Testing of TSV and MicroBump Devices by Direct Connection Benjamin N. Eldridge, Senior VP, R&D and CTO, FormFactor Inc.
Testing of Through Silicon Via (TSV) or Micro-Bump (MB) devices by physical connection through the TSVs presents unique challenges due to the very high density of the connections, and the potential impact of contact testing on subsequent assembly steps. In addition, the very high signal counts that are the main benefit of TSV connection schemes make conventional wafer probing, particularly for memory devices which demand very high parallelism at production wafer sort, largely impractical. We will present results to date on probing and testing of TSV structures, and share our view on the role that contact test at the wafer, die and die stack level will play in the future of TSV and MB based system assembly.
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3D IC Test Cost Effective Solution Mr. Sam Ko, Deputy Director, KYEC
ICs of 3D integration have developed for a few years and have implemented in the applications of MEMs, image sensors, and memory. With more and more application products coming out, the 3D IC tests of characterization and mass production are given weight to implementation and cost effective for the necessary of economic scale market. This presentation is embarked on the view of testing house KYEC to reveal the proper 3D IC test solution for mass production.
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