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SiP Global Summit 3D IC Technology Forum |
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For online registeration, please click "Register Now"! |
Thursday, September 8, 2011
08:30 –17:30
201 ABC, 2F, TICC
Event Fee : Free (Pre-registration is required)
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Theme : Embracing the Era of 2.5D & 3D ICs
Chair : Co-chairs : 2. Dr. YJ Chan, Vice Chairman of SEMI Taiwan PKG&TEST Committee / VP & EOL General Director, ITRI 4. Dr. Rolf Aschenbrenner, President of the IEEE-CPMT, Deputy Director of Fraunhofer IZM
Morning Session Moderator : Dr. YJ Chan, Vice Chairman of SEMI Taiwan PKG&TEST Committee / VP & EOL General Director, ITRI Mr. Rudi Cartuyvels, VP and GM Process Technology Unit, IMEC |
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Co-organized by |
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Technical Sponsored by |
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Outline : |
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08:30 – 09:00 |
Registration |
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09:00 – 09:10
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Welcome Remarks 2. Dr. Rolf Aschenbrenner, President of the IEEE-CPMT, Deputy Director of Fraunhofer IZM |
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09:10 – 09:40 |
Opening Speech - Embracing the Era of 2.5D & 3D ICs Dr. Ho-Ming Tong, Chairman, SEMI Taiwan PKG&TEST Committee / General Manager & Chief R&D Officer, ASE Group |
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09:40 – 10:10 |
Mr. Victor Peng, Senior Vice President, Programmable Platforms Development, Xilinx, Inc. |
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10:10 – 10:40 |
Prof. Kanji Otsuka, Emeritus Professor, Special Advisor Collaborative Research Center, Meisei University |
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10:40 – 11:10
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PlayStation 3 Leads Stereoscopic 3D Entertainment World Mr. Teiji Yutaka, SVP, SONY Computer Entertainment, Inc. |
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11:10 – 11:40 |
Mr. Takayuki Watanabe, VP of TSV Packaging Development Group, TD Office, Elpida Memory,Inc. |
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11:40 – 12:10 |
Paradigm Shift and Foundry Integration Dr. C.H. Yu,Sr. Director of Integrated Interconnect and Package Division, R&D, TSMC |
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12:10 – 13:50 |
Lunch Break |
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13:20 – 13:50 |
Afternoon Registration |
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13:50 – 14:00 |
Welcome Remarks 1. Executive from SEMI |
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14:00 – 14:30 |
The Market Challenges of Manufacturing Convergence: Going Vertical Mr. Jim Walker, Research VP, Gartner Inc. |
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14:30 – 15:00 |
3D IC with TSV Integration: Moving from PowerPoint to Production Mr. Scott Jewler, Chief Engineering, Sales, and Marketing Officer, Powertech Technology Inc. |
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15:00 – 15:30
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3D TSV Test: Myths, Challenges, and Solutions Dr. Erick Volkerink, CTO, Verigy |
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15:30 – 16:00 |
Materials Perspective for 3D Semiconductor Packaging Dr. Itsuo Watanabe, Executive Officer, General Manager, Tsukuba Research Laboratory, Hitachi Chemical |
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16:00 – 16:30 |
R&D Institution Perspective: 2.5D & 3D IC Research & Development Dr. Rolf Aschenbrenner, President of the IEEE-CPMT, Deputy Director of Fraunhofer IZM |
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16:30 – 17:00 |
Organization of 3D Activities at Léti. The role of R&D 200 and 300 mm Lines Dr. André Rouzaud, VP of Heterogeneous Silicon Integration Department, LETI |
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17:00 – 17:30 |
Standardization requirements for 3D-TSV system integration Mr. Eric Beyne, Scientific Director, Advanced Packaging and Interconnect Technology, IMEC |
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17:30 |
Adjournment |
● Programs are subject to change without prior notice.
● All presentations will be conducted in English.
Chair's Introduction:
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Dr. Ho-Ming Tong, Chairman, SEMI Taiwan PKG&TEST Committee / GM & CTO, ASE Group
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Co-Chairs' Introduction:
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Dr. Shen-Li Fu, Vice Chairman of SEMI Taiwan PKG&TEST Committee / President, I-Shou University
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Dr. YJ Chan, Vice Chairman of SEMI Taiwan PKG&TEST Committee / VP & EOL General Director, ITRI
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Dr. Kuo-Ning Chiang, Member of SEMI Taiwan PKG&TEST Committee / Distinguished Professor, Dept, of Power Mechanical Engr., NTHU / Director, Advanced Packaging Research Center / ASME Fellow
−Ph.D., ME of Georgia Institute of Technology −M.S., ME of University of South Carolina −B.S. National Cheng Kung University ●Experience −Present: - Director of National Center for High-Performance Computing −Present: - Distinguished Professor, National Tsing Hua University −Present: - Chairman of IMAPS - Taiwan −Present: - Director, Advanced Packaging Research Center, NTHU −Present: Editor-in-Chief, IEEE Transactions on Components, Packaging and Manufacturing Technologies −ASME Fellow −Associate Editor, IEEE Transactions on Advanced Packaging −Associate Editor, Journal of electronic package － ASME Transactions −Associate Editor, Journal of Mechanics −IEEE Senior Member −Engineering Director of ERSO/ITRI (2003-2005) −Secretary-General of ASME Taiwan Section (2002-2005) −Chairman of Key Application Committee – ERSO/ITRI (2005) −Director of R&D Dividion, NCHC (1993-1998) −Board Member of IMAP (International Microelectronics and Packaging Society) - Taiwan −Board member of KingPak Technology Inc. −Board member of Argosy Research Inc.
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Dr. Rolf Aschenbrenner, President of the IEEE-CPMT, Deputy Director of Fraunhofer IZM
● Since September 2010 and from 2000 – 2006 Deputy Director of Fraunhofer IZM ● Since January 2010 IEEE CPMT President ● Since 2008 Head of Department “System Integration and Interconnection Technologies” at Fraunhofer IZM ● 12 January, 2005 he was awarded the “iNEMI International Recognition Award”
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Morning Session Moderator :
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Dr. YJ Chan, Vice Chairman of SEMI Taiwan PKG&TEST Committee / VP & EOL General Director, ITRI
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Afternoon Session Moderator :
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•Mr. Rudi Cartuyvels, VP and GM Process Technology Unit, IMEC
Rudi Cartuyvels graduated with a MS EE degree from the K.U.Leuven in 1990 and started his career at IMEC in the same year. He has worked on computer experiment modeling for design and optimization of CMOS technology using TCAD-based simulation tools and was responsible for transferring IMEC’s computer experiment modeling and optimization techniques to a commercial platform in the field of vibro-acoustic engineering. In 1998, he was appointed business development manager for IMEC’s semiconductor process technology division. In 2001, he became director of IMEC’s interconnect technology department responsible for Cu and low-k technology scaling. Packaging and system integration were added to his responsibilities in 2007. In 2009 he became vice president and general manager of Process Technology. Since 2011 he is vice president R&D Business Lines. Rudi Cartuyvels is a member of the IITC Program Committee.
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Welcome Remarks Speaker Introduction:
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Mr. Jonathan Davis, President, Global Semiconductor Business
Jonathan Davis is a member of the Global Executive Team of SEMI, the global industry association serving 2,000 member companies that provide equipment, materials and services used to manufacture semiconductors, displays, nano-scaled structures, micro-electromechanical systems (MEMS) and related technologies.
Since September 2007, he serves as Executive Vice President with oversight responsibility for the association's global exposition operations, corporate marketing, creative services, communications and public relations, information products and publishing functions as well as the acclaimed SEMI Industry Research and Statistics operations and Environmental Health and Safety Department.
Prior to his current position, Davis was in charge of Global Marketing and Communications, having advanced over a prior decade through the positions of manager, director, senior director and vice president with marketing, communications and public relations duties.
Before holding positions in marketing, communications and PR, Davis managed the SEMI Membership Department. Davis joined SEMI in 1992 to initiate the organization's Outreach Program, through which he conducted and reported on SEMI member company visits throughout North America and informed management about customer requirements and satisfaction.
Before joining SEMI, Davis worked for nine years at HNTB, a national architecture and engineering firm. He earned a 5-year architecture degree from the Kansas State University College of Architecture and Design and studied at the University of Missouri at Columbia School of Journalism. Davis is a member of the American Society of Association Executives and the Public Relations Society of America.
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Speakers' Introduction:
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Mr. Victor Peng, Senior Vice President, Programmable Platforms Development, Xilinx, Inc.
● Leads a global team responsible for development and delivery of programmable platforms including FPGA silicon, software, IP, and boards ● Served as Corporate VP of the Graphics Products Group (GPG) silicon engineering with AMD ● Held key engineering leadership roles at TZero Technologies, MIPS Technologies, SGI, and Digital Equipment Corporation ● BSEE from Rensselaer Polytechnic Institute & a ME in EE from Cornell University and holds four US patents
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Prof. Kanji Otsuka, Emeritus Professor, Special Advisor Collaborative Research Center, Meisei University
● Bachelor from Kyoto Institute of Technology, Doctor from Tokyo Institute of Technology ● Semiconductor R&D, Hitachi Co., Ltd. ● Main frame R&D, Hitachi Co., Ltd ● Professor, Director, Dean, Meisei University ● BoG IEEE/CPMT, President of Japan Institute of Electronics Packaging, Fellow IEEE, Director of IMSI ● Emeritus Prof. Advisor Meisei Univ., Invited Prof. Osaka Univ., Guest Instructor Univ. of Tokyo ● Over 100 papers w/o referee, over 50 patents ● Job function : System packaging so-called concurrent total system design
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Mr. Teiji Yutaka, SVP, SONY Computer Entertainment, Inc.
●1988 Joined Sony Information Research Lab Worked on interactive entertainment using the computer technology
●1993 Joined Sony Computer Entertainment Inc. Participated in the development team for the PlayStation®, PlayStation®2 and PlayStation®3 systems
●2007 SVP, Sony Computer Entertainment Inc. Responsible for Software R&D including the stereoscopic 3D technology
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Mr. Takayuki Watanabe, VP of TSV Packaging Development Group, TD Office, Elpida Memory,Inc.
●TSV Pj. ,Elpida Memory ●BEOL, Akita Elpida Memory ●Semiconductor Memory, NEC ●Speaker of ICEP 2009
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Dr. C.H. Yu, Sr. Director of Integrated Interconnect and Package Division, R&D, TSMC
• Establish TSMC Cu/low-K technology. Deliver the first Cu/FSG, Cu/Low-k(K=3.0) in industry at 0.13 micron node, first Cu/ELK(K=2.6) at 45nm node to • Received National Outstanding Invention Award (CAITA), Outstanding Scientific and Technological Worker Award (National Science Council), Industrial Technology Achievement Award (MOEA), National Outstanding R&D Managers (CPMA), and Outstanding Engineer Award (Chinese Institute of Engineer).
Integration of Interconnect and Package Technology at TSMC including intra- and inter-chip interconnect, bumping/assembly and TSV/3D-IC technologies.
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Dr. Luc Van den hove, CEO, IMEC
Luc Van den hove is President and Chief Executive Officer (CEO) of imec since July 1, 2009. Before holding this position he was Executive Vice President and Chief Operating Officer. He joined imec in 1984, starting his research career in the field of silicide and interconnect technologies. In 1988, he became manager of imec’s micro-patterning group (lithography, dry etching); in 1996, Department Director of Unit Process Step R&D; and in 1998, Vice-President of the Silicon Process and Device Technology Division. In January 2007, he was appointed as imec's EVP & COO. Luc Van den hove received his Ph.D. in Electrical Engineering from the University of Leuven, Belgium. He has authored or co-authored more than 100 publications and conference contributions.
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Mr. Jim Walker, Research VP, Gartner Inc.
● Surface Mount Packaging Marketing Manager – National Semiconductor ● Director of Q.A. – E.I. DuPont ● Co-founder and President Emeritus - Surface Mount Technology Association (SMTA) ● Past Advisory Board Member – Surfect Technologies and Bridgewave Communications ● Past Advisory Board Member – Advanced Packaging Magazine ● Board of Advisors– Micro Electronic Packaging/Test Engineering Council (MEPTEC) ● Guest Lecturer – University of California, Berkeley
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Mr. Scott Jewler, Chief Engineering, Sales, and Marketing Officer, Powertech Technology Inc.
● Sr. VP, Sales and Applications Enginineering, Ultratech ● Chief Strategy Officer, STATS ChipPAC ● President, Amkor Technology Taiwan ● Sr. VP, Assembly Business Unit, Amkor Technology ● 4 US Patents in IC packaging ● BS in Mechanical Engineering, Clemson University
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● Senior Director of Technology and Chief Scientist, Verigy 2008-2010 ● General Chair and Founder of ATEVision 2020 for Semiconductors (ITRS) ● Consulting Assistant Professor, Electrical Engineering Department, Stanford University, 2004-2010 ● PhD Electrical Engineering, Stanford University
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Dr. Itsuo Watanabe, Executive Officer, General Manager, Tsukuba Research
● Dr. Itsuo Watanabe is currently an Executive Officer and a General Manager of Tsukuba Research Laboratory of Hitachi Chemical Co., Ltd.. He joined Hitachi Chemical Co., Ltd. in 1982 and had conducted research and development on high performance polymeric materials for more than 20 years.
● He received his MS degree in chemistry from Utsunomiya University and his PhD degree in polymer science from Kyoto University.
● He serves as a member of the technical committee of the international conferences such as international conference on “Electronics Packaging”. He served as a general chairman of 2005 ICEP. He has presented a number of invited papers at international conferences in the area of semiconductor packaging technologies.
● He received the Award of the Society of Polymer Science, Japan for the research and development of anisotropic conductive films in 2003.
● He also received John A. Wagnon Technical Achievement Award of International Microelectronics and Packaging Society for outstanding technical contributions to microelectronics technology in 2005.
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Dr. Rolf Aschenbrenner, President of the IEEE-CPMT, Deputy Director of Fraunhofer IZM
● Since September 2010 and from 2000 – 2006 Deputy Director of Fraunhofer IZM ● Since January 2010 IEEE CPMT President ● Since 2008 Head of Department “System Integration and Interconnection Technologies” at Fraunhofer IZM ● 12 January, 2005 he was awarded the “iNEMI International Recognition Award”
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Dr. André Rouzaud, VP of Heterogeneous Silicon Integration Department, LETI
● Since 2004, deputy-VP µsystems and heterogeneous integration at Léti/ Minatec. ● Director of Laboratory of Surface Processes at CEA/Liten ● Head of Group Crystal Growth activities at CEA/Liten. ● > 30 publications in the field of experimental and theoretical crystal growth, process modelling, sputtering technologies ● Filed 11 patents
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Mr. Eric Beyne, Scientific Director, Advanced Packaging and Interconnect Technology, IMEC
Eric Beyne is program director of the advanced packaging and interconnect research Centre, APIC, at imec. The APIC team performs R&D in the field of. high-density interconnection and packaging techniques focused on “system-in-a-package” integration, 3D-interconnections, wafer level packaging, rf front-end design and technology using integrated passives and rf-MEMS as well as research on packaging reliability including thermal and thermo-mechanical characterization.
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Presentation Abstract:
| Keynote Speech - Realizing a Two Million Logic Cell 28nm FPGA with Stacked Silicon Interconnect Technology
Mr. Victor Peng, Senior Vice President, Programmable Platforms Development, Xilinx, Inc.
FPGA logic capacity is doubling with successive process technology nodes and has enabled systems on chip (SOC) of greater complexity to be implemented using FPGAs. The industry’s need for greater integration at the 28nm node and beyond continues and indeed is increasing for many applications. This talk will outline how Xilinx is realizing a 2M logic cell 28nm hi-k metal gate FPGA product using Stacked Silicon Interconnect (SSI) technology. SSI technology utilizes micro-bump and Through-Silicon Via (TSV) technologies, with multiple active die on a passive interposer to enable integration beyond what’s possible with monolithic die or Multi-Chip Modules (MCMs). An overview of the design, technology, and supply chain issues will be given, as well as potential future directions.
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How to Make True 3D-TSV IC Application--Spreading 3D-TSV IC Technologies, But Not Followed By Major Applications
3D-TSV IC technologies are already recognized as most emergency issues. However we still not make suitable application as major product with balanced cost-performance. Recent technology for the TSV interconnections can provide the 5um for the diameter that is still too much large. It must have the surround area of least 7um dia. This runs to waste area for over 2000 transistors, when the transistor cell size is around 150nm square for 32nm node process. Such geometry design is hard to play for replace from horizontal wiring to vertical interconnections for system consideration. Therefore, the trend shifts to IC chips on a wiring Si interposer with TSVs, which is not true 3D-TSV IC system. We should find efficient TSV geometry system in active area even in the area wasting. It is not peripheral assignment TSVs in current bonding area. I will offer the several concepts for the efficient TSV geometry systems such as interleave clusters circuit, saving power structure and etc.
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PlayStation 3 Leads Stereoscopic 3D Entertainment World Mr. Teiji Yutaka, SVP, SONY Computer Entertainment, Inc.
PlayStation3, a world famous computer entertainment system, has been updated to support stereoscopic 3D contents.
In this session, I will describe why stereoscopic 3D gaming is the killer application of 3D contents, Recent update of Sony Computer Entertainment’s initiative on stereoscopic 3D, Future of 3D interactive entertainment with exciting examples, And our strategy to bring new experience to our platform through stereoscopic 3D technology.
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Mr. Takayuki Watanabe, VP of TSV Packaging Development Group, TD Office, Elpida
● To approach different die function and design of Wide I/O DRAM for mobile application and computing one. ● To be possible of interposer for 2.5D to interconnect between processor and stacked TSV DRAMs. ● To take DfX approach as DfT, DfM etc on die design to support TSV improvement as stacked KGD DRAM yield. ● To clarify and establish mutual triangle relation via final quality assurance between customer, processor and DRAM vendor. ● To standardize TSV pin/array function and location of DRAM at first and then several miscellaneous items. ● To be potential of creating new TSV foundry business in case of Via Last process.
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Paradigm Shift and Foundry Integration Dr. C.H. Yu,Sr. Director of Integrated Interconnect and Package Division, R&D, TSMC
In semiconductor world, there is a new paradigm shift from chip scaling to system scaling to meet the ever increasing electronic system demands in power saving, performance and functionality (including memory bandwidth) increase, form factor improvement and cost reduction. This shift is also triggered by the growing concerns for industry to sustain Moore’s Law.
This presentation will discuss the approaches to resolve these issues.
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The Market Challenges of Manufacturing Convergence: Going Vertical Mr. Jim Walker, Research VP, Gartner Inc.
Even as semiconductor packaging becomes more “front end” oriented in its solutions to industry’s challenges, it is still seen as the manufacturing cost and performance “gatekeeper” when it comes to new product development. The smaller, lighter, faster, cheaper mantra continues, even as packaging and the emerging 3D approaches have become an enabler of Moore’s Law. The wafer, package and board are developing into more of one continuous, overlapping process. How the industry adapts to this convergence of manufacturing will be just as critical, if not more, than that seen by the convergence of the product and its applications.
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3D IC with TSV Integration: Moving from PowerPoint to Production Mr. Scott Jewler, Chief Engineering, Sales, and Marketing Officer, Powertech Technology Inc.
3DIC market drivers and timing of transition for volume production.
3DIC stacked devices using TSV interconnect technology are moving to volume production. Real applications using this technology will be presented together with discussion of the current status of related assembly and test technology required to bring these products to market.
Collaboration model between OSAT, Foundry, and IDM will be shared and the value of this model to enable 3DIC products to go to market will be analyzed
The differences in the technical and supply chain model for homogeneous memory 3DIC’s and those incorporating heterogeneous memory and logic will be presented and industry solutions proposed to facilitate further successful integration
The need for standardization will be presented along with specific activity related to testing of 3DIC
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Dr. Erick Volkerink, CTO, Verigy
The 3D TSV revolution is happening! After a slow start, the solution for increased circuit density, lower power consumption and improved bandwidth appears to be on its way for adoption in the industry. While a lot of test challenges have been addressed with innovative solutions, there still remain many to be tackled to fully adopt 3D TSVs. This paper provides an overview of the state-of-the-art in 3D TSV test, presents the major test challenges as well as the myths and misconceptions, and introduces new test solutions and concepts.
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Materials Perspective for 3D Semiconductor Packaging Dr. Itsuo Watanabe, Executive Officer, General Manager, Tsukuba Research Laboratory, Hitachi Chemical
3D semiconductor packeging technologies such as wire bonding die-satcked Chip Size Package(CSP), Package on Packege(POP) and Through Silcon Via(TSV) technology have been of much interest because they provide the highest packaging density and electrical performance among conventional semiconductor packaging technologies. 3D semiconductor packaging technology is the key technologies to realize a highly integration of logic and memory devices. Therefore, recently the 3 D semiconductor packaging technologies have been widely used in varios devices such as image sensor. logic and maemory devices. The high parfoemance matrials such as RDL materials, underfill, die bonding films, subtrate materials are very issential in improving the 3D semiconductor packaging technologies. In this talk, materials trends and challenges for 3D semiconductor packaging tecdhnologies are discussed.
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R&D Institution Perspective: 2.5D & 3D IC Research & Development Dr. Rolf Aschenbrenner, President of the IEEE-CPMT,Deputy Director of Fraunhofer IZM
The long term vision of 3D Integration is miniaturization of the entire electronic system using silicon for ICs, packages and boards. This is envisioned to be accomplished by miniaturization of all system components such as power supplies, IC packages, system boards, passive components, active components, system interconnections, thermal structures and heat sinks and external connections. Semiconductor roadmaps predict that the advancement in silicon technologies will follow the well known “Moore’s law” in the next decade, too. However, for future multifunctional systems in many cases the cost efficient IC standard technologies cannot be applied. Non-digital and often MEMS functions require alternative materials, specific assembly processes and application environment oriented packaging solutions. Therefore future system integration often will be a combination of “More Moore” - or “system on chip (SoC)”-solutions and advanced assembly and packaging technologies, for example “system in package (SiP)”. Main advantages of this approach is performance improvement and application flexibility for different product groups, manufacturability with established processes and a high potential for cost reduction.
The presentation describes the strategy as well as advantages and disadvantages concerning advanced 3D packaging solutions at wafer level. Technology background, implementation conditions and exploitation experiences as well as application examples will be presented.
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Organization of 3D Activities at Léti. The role of R&D 200 and 300 mm Lines Dr. André Rouzaud, VP of Heterogeneous Silicon Integration Department, LETI
In a first time confined to labs and then R&D centers, 3D integration technologies have now gained maturity and are now penetrating the industrial world. Within this context, these R&D centers are now approached to back the industrial developments. Under the associated constraints of swift product development, prototyping, and short time-to-market, research tools and equipments are now no longer efficient nor relevant. In light of these observations, Léti has decided to massively invest in a 3D integration 300 mm line, inaugurated January 2011, to efficiently valorize its former promising developments and efficiently accompany its industrial partners. This talk presents Léti’s 3D general approach, both in terms of: - R&D approach with the validation of some few generic integration schemes based on validated technological blocks (toolbox), able to cover a wide spectrum of industrial applications and needs (heterogeneous integration, 3D WLP, 3D IC…), - the associated technological roadmaps for the central toolbox cornerstones (vias, bonding, connections, RDL…), - the strategic alliances set with key equipments manufacturers and materials suppliers to efficiently achieve the roadmaps objectives, and more generally with the different actors of the evolving supply chain. - the present status and roles of its prototyping lines in the context of swift market evolutions.
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Standardization requirements for 3D-TSV system integration Mr. Eric Beyne, Scientific Director, Advanced Packaging and Interconnect Technology, IMEC
As 3D-TSV stacking technologies are nearing maturity and market introduction, the importance of compliance with and availability of standards for these novel technologies is sharply rising. 3D system integration is a field that affects almost every aspect of the microelectronics supply chain, from design, through silicon technology to packaging and assembly. Intimate collaboration between the various partners in the supply chain is essential and clear agreements at the hand-over points will be required. These are the major driving forces for the development of new standards.
The various aspects related to standardization that will be discussed are:
· TSV processing. A strict standardization is probably not required in this area. However, technology roadmaps are important, in order to allow an efficient equipment and materials supplier base for TSV process technology to be developed. Compliance with existing standards is to be preferred over development of new standards.
· Thin wafer handling. This is an important issue at the hand-over point between the stages: (i) TSV processing; (ii) backside wafer processing; (iii) testing and (iv) stacking.
· High density microbumps. Two aspects require attention: the µbump pitch roadmap and the selection of surface materials.
· Standard components (such as wide-I/O memory dies). Pin location and pin assignment of functionality are important for applications that require reuse of components across various applications and/or multi-sourcing of such components.
· Testing. Especially for extending 2D design for test architectures to 3D, the IEEE P1838 Working Group on 3D test access architecture standardization and JTAG IEEE 1149.1 are crucial.
· Design flow. Essential information for the system designer will need to come from the various suppliers in the 3D process: KGD data, electrical models, geometrical models, PDKs for TSV and µbump connections, models for the µbump and package level interconnects. Moreover, in order to enable system-level simulation of the 3D stack, compact thermal and mechanical models need to be exchanged between various design environments and tools. Standardized open interchange formats must be used in order to facilitate this.
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