SiP Global Summit

Embedded Substrate Forum

 For online registeration, please click "Register Now"!  

 

 Friday, September 9,  2011
08:30 –12:25
201 BC, 2F,  TICC 
Event Fee : Free (Pre-registration is required)

 

 

Theme :  Bridging the Last Mile of Heterogeneous Integration

Chair :
Dr. Kuo-Ning Chiang, Distinguished Professor, Dept, of Power Mechanical Engr., Director, Advanced Packaging Research Center, ASME Fellow, NTHU

 

Co-chairs :
1. Mr. Walter Jau, Director, Corporate R&D/Corporate Engineering, ASE Group

2. Dr. Wei-chung Lo, Director, Package Technology Div./EOL, ITRI

3. Dr. Kwang-Lung Lin, Professor, Dept. of Materials Science and Engineering, National Cheng Kung University

 
              

 

Organized by

  

  

 

  

 

Sponsored by

  

  

 

  

 

  

 

Technical Sponsored by

 

 

 

 

 

Outline :
To enable new user experiences, more functions are being incorporated in microelectronics at an accelerated rate.   To date, this has been accomplished by function integration through SoC at the IC level, as well as an ever-larger array of new SiPs such as 2.5D & 3D ICs at the package component level.  Although embedded passives has successfully made its way into host cards, embedding passives in the package substrate is just beginning to dawn for applications ranging from consumer electronics to routers.  Despite much fan fare, embedded active in substrate remains elusive in implementation and will grow in importance with time.  A flurry of activities has been spawned by leading companies in the recent past in order to enable embedded technologies in the substrate which remains the last frontier of heterogeneous integration in SiP packaging.  In this symposium, leaders from key segments of the eco-system will share their perspectives and experiences covering readiness for commercialization and what the future has in store for us in this emerging area of SiP.

  
              



 

 

Agenda:

 

 

 

08:30 – 09:00

Registration

09:00 – 09:10

Welcome Remarks 

1. Mr. Jonathan Davis, Global Semiconductor Business Executive Vice President, SEMI

2. Dr. Kuo-Ning Chiang, Distinguished Professor, Dept, of Power Mechanical Engr., Director, Advanced Packaging Research Center, ASME Fellow, NTHU

09:10 – 09:45

Trends in Embedded Substrates:  Technology, Markets, and Applications

Ms. E. Jan Vardaman, President & Founder, TechSearch International, Inc. 

09:45 – 10:20

Overview for Embedding Discrete/Active Technologies from Mobile Device Perspective

Dr. Takayosi Katahira, Specialist of PWB & Packaging Technology, Devices R&D, Nokia Corporation  

10:20 - 10:40

Break Time

10:40 – 11:15

3D Integration Technology Focused On Device Embedded Substrate
 

Mr.  Hajime Tomokaga, Professor Fukuoka University

11:15 – 11:50

High Yield Rate Manufacturing Technology for EDS/EPS 

Mr. Bruce Su, VP, ASE Group

11:50 – 12:25

Advanced Materials for Embedded Substrate

Mr. Makoto Kato, Senior Researcher, Hitachi Chemical Co., Ltd.

12:25

Adjournment

Programs are subject to change without prior notice.
All presentations will be conducted in English.

Chair's Introduction:

 

Dr. Kuo-Ning Chiang, Member of SEMI Taiwan PKG&TEST Committee / Distinguished Professor, Dept, of Power Mechanical Engr., NTHU / Director, Advanced Packaging Research Center / ASME Fellow


Educational Background 

Ph.D., ME of Georgia Institute of Technology

M.S., ME of University of South Carolina

B.S. National Cheng Kung University

Experience 

Present:  - Director of National Center for High-Performance Computing  

Present:  - Distinguished Professor, National Tsing Hua University  

Present:  - Chairman of IMAPS - Taiwan

Present:  - Director, Advanced Packaging Research Center, NTHU

Present: Editor-in-Chief, IEEE Transactions on Components, Packaging and Manufacturing Technologies

ASME Fellow

Associate Editor, IEEE Transactions on Advanced Packaging

Associate Editor, Journal of electronic package - ASME Transactions

Associate Editor, Journal of Mechanics

IEEE Senior Member

Engineering Director of ERSO/ITRI (2003-2005)

Secretary-General of ASME Taiwan Section (2002-2005)

Chairman of Key Application Committee – ERSO/ITRI (2005)

Director of R&D Dividion, NCHC (1993-1998)

Board Member of IMAP (International Microelectronics and Packaging Society) - Taiwan

Board member of KingPak Technology Inc.

Board member of Argosy Research Inc. 

 

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Co-Chairs' Introduction: 

 

Mr. Walter Jau, Director, Corporate R&D/Corporate Engineering, ASE Group

 

Ph.D. Candidate, N.C.K.U.

R&D Manager, ASE Material

Project Manager, ASE-KH

Owned 31+ patents

 

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Dr. Wei-Chung Lo, Director of package technology division, ITRI

Director of package technology division, ITRI
M.S. degree and Ph.D. in Chemistry from National Taiwan University, Taiwan
 Wharton school AMP 2010, US
 Executive Secretary of 3DIC consortium(Ad-STAC)
 Program Committee Chair of International Microsystems, Packaging, Assembly and Circuits Conference(IMPACT conference 2009)
 Chair of Advanced Microsystem and Packaging Alliance, the largest package alliance in Taiwan (AMPA)
 holds 8 patents and has published over 20 papers

 

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Dr. Kwang-Lung Lin, Professor, Dept. of Materials Science and Engineering, National Cheng Kung University

 

Professions:

Post Doc - Ames Lab/DOE (Iowa State University) 1984/2~ 1985/1.

Associate Professor - Department of Materials Science and Engineering, NCKU,1985/2 ~ 1989/7

Professor - Department of Materials Science and Engineering, NCKU, 1989/7 ~ present

Chairman - Department of Materials Science and Engineering, NCKU, 1991/8 ~ 1994/7

Deputy Director - Engineering and Technology Promotion Center, 1997/8 ~ 1999/8

Director - Precious Instrument Center - NCKU / National Science Council,1999/8~2002/7

Program Coordinator - Metal and Ceramics Program, National Science Council, 2001/12 ~ 2004/11

Director - Institute of Nano Science and Technology/ NCKU, 2004/10~2004/12

Chairman - Institute of Micro Electromechanical System / NCKU 2004/8~2004/12

Director General - Department of International Cooperation / National Science Council, R.O.C., 2005/1~2007/12

Society Member - Electrochemical Society, IEEE - CPMT (Senior Member), ASM, TMS, AESF, Chinese Society of Materials (Taiwan)

Vice CEO – ITRI South (2009/2 ~ 2010/1)

  Vice CEO – ITRI South (2010/2 ~ 2011/1)

 

Awards, Honors:

  Reviewer, Materials Chemistry and Physics.(1995~)

  Biographee - Who’s Who in the World ,Marquis Who’s Who (1996~)

  Outstanding Research Award, NSC (1997, 1999)

  Best Paper Award - Silver Medal, AESF (1997)

  Outstanding Engineering Professor, Chinese Engineer Society (Taiwan) (1997)

  Biographee - Who’s Who in Science and Engineering, Marquis Who’s Who (1997~)

  Biographee - Who’s Who in Finance and Industry, Marquis Who’s Who (1997~)

  Biographee - Dictionary of International Biography, Vol. XXVI, International Biographical Center, Cambridge, England (1997~)

  Biographee - The International Directory of Distinguished Leadership, 7th Edition - 1997, American Biographical Institute, North Carolina, U.S.A, (1997~)

  Biographee - Who’s Who in Asia and the Pacific Nations, IBC (1999 ~)

  Biographee - Asia/Pacific Who’s Who, p.478, Vol. III, - 2000, Rifacimento International (2000~)

Editor - Materials Chemistry and Physics (2003/6 ~ present)

 2005 IEEE Senior Member

 2005侯金堆傑出榮譽獎 (金屬冶煉類)

  2007 Materials Research Society-Taiwan(MRS-T) Outstanding Service Award

  2010 Materials Research Society-Taiwan(MRS-T) Fellow

 2011 IEEE Fellow   

 

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Welcome Remarks Speaker Introduction:

Mr. Jonathan Davis, President, Global Semiconductor Business
Executive Vice President, SEMI

 

 

Jonathan Davis is a member of the Global Executive Team of SEMI, the global industry association serving 2,000 member companies that provide equipment, materials and services used to manufacture semiconductors, displays, nano-scaled structures, micro-electromechanical systems (MEMS) and related technologies.

 

Since September 2007, he serves as Executive Vice President with oversight responsibility for the association's global exposition operations, corporate marketing, creative services, communications and public relations, information products and publishing functions as well as the acclaimed SEMI Industry Research and Statistics operations and Environmental Health and Safety Department.

 

Prior to his current position, Davis was in charge of Global Marketing and Communications, having advanced over a prior decade through the positions of manager, director, senior director and vice president with marketing, communications and public relations duties.

 

Before holding positions in marketing, communications and PR, Davis managed the SEMI Membership Department. Davis joined SEMI in 1992 to initiate the organization's Outreach Program, through which he conducted and reported on SEMI member company visits throughout North America and informed management about customer requirements and satisfaction.

 

Before joining SEMI, Davis worked for nine years at HNTB, a national architecture and engineering firm. He earned a 5-year architecture degree from the Kansas State University College of Architecture and Design and studied at the University of Missouri at Columbia School of Journalism. Davis is a member of the American Society of Association Executives and the Public Relations Society of America.

 

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Speakers' Introduction:

 

Ms. E. Jan Vardaman, President & Founder, TechSearch International, Inc.

 

● Founded TechSearch International in 1987 providing analysis on

  technology and market trends in semiconductor packaging and materials

● Served on the corporate staff of Microelectronics and Computer

  Technology Corp. 1984-87

● Co-author of How to Make IC Packages, published by Nikkan Kogyo

  Shinbunsha

● Columnist with Printed Circuit Design & FAB/Circuits Assembly Magazine

● Member of IEEE CPMT, IMAPS, MEPTEC, SMTA, and SEMI

 

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Dr. Takayosi Katahira, Specialist of PWB & Packaging Technology, Devices R&D, Nokia Corporation

 

Katahira belongs to PWB and Packaging Solutions, CTO Organization in Nokia

He is responsible for both printed circuit and packaging development, and has been in charge of various tasks, e.g. thermal design, any layer PCB, fine pitch BGA, Fan-Out WLP, co-design and embedded technologies since he joined Nokia in 1999. 

Prior to joining Nokia, he was an R&D engineer for IC-packaging in Motorola for 7 years.

He acquired a Ph.D. in System Mechanics  in Yokohama National University

 

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 Mr. Hajime Tomokaga, Professor Fukuoka University
  

• Former President, Japan Institute of Electronics Packaging  

   (2009.06-2011.05)
• President, Asia Semiconductor Trading Support Association

   (ASTSA)
• President, NPO Semiconductor Technology Marketing (STM)
• Chairman, International Workshop on Microelectronics

   Assembling and Packaging (MAP)
• Project manager, National project on System Integration

   Platform at Fukuoka

 

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Mr. Bruce Su, VP, ASE Group 

 

 

● VP, Operation , ASE
● Plant manager , Substrate
● Production manager , Lead Frame
● Engineer , ITRI
● Master ,Sun-Yet-Sen University
● Speaker, Samsung/Toshiba tech forum
● Speaker ,ASE Tech forum

● Owned 31 patents

 

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Mr. Makoto Kato, Senior Researcher, Hitachi Chemical Co., Ltd.



● Developing HDI materials since 2010-
● Engineering Manager in US, 2007-2010
● Developing High Tg core materials, 2000-2007 
● Process engineer in Laminates manufacturing, 1992-2000 
● Developing  materials for multi layer boards, 1989-1992

 



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Presentation Abstract:

Trends in Embedded Substrates:  Technology, Markets, and Applications

Ms. E. Jan Vardaman, President & Founder, TechSearch International, Inc.

 

Technology to form passive components on internal layers and to place active or passive devices in a substrate has been available for more than twenty years, but implementation has been limited.  Changing market needs and significant improvements in the technology has resulted in a resurgence of interest.  Drivers include size reduction, increased function, lower voltages, increasing current, higher frequencies, reduced weight, improved reliability, and reduced cost.  Embedded components are found in many different configurations.  Some companies will embed active components in the substrate using a lamination process.  This can take the form of bare die or a wafer level package.  Some applications use embedded formed resistors or capacitors, while others embed discrete passive components.  In this presentation, trends in each of the areas will be described including advantages/disadvantages as well as drivers for adoption.

 

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Overview for Embedding Discrete/Active Technologies from Mobile Device Perspective

Dr. Takayosi Katahira, Specialist of PWB & Packaging Technology, Devices R&D, Nokia Corporation

 

There are various embedding technologies in industry, and in this presentation, embedding discrete/active for mobile devices are focused except for thin film capacitor/resistor.

 

In terms of mobile device, applications for embedding discrete/active can be classified into three, packaging substrate, module substrate and mainboard. Those embedding technologies are discussed from the three aspects, and the future requirements are illustrated.

 

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3D Integration Technology Focused On Device Embedded Substrate

Mr.  Hajime Tomokaga, Professor Fukuoka University

 

The device embedded substrate is one of key technologies on 3D integration as well as 

through-silicon-via (TSV) technology. The national project on 3D integration has been running in

Fukuoka since 2002. In March, 2011, a new research institute on 3D integration was established

in Fukuoka. Starting from design technology, proto typing, evaluation and test technologies on

device embedded substrate are being developed as a consortium project. Japan Electronics

Packaging and Circuits Association (JPCA),on the other hand, has been publishing the standard

on device embedded substrate EB-01 since 2008. The research project is in conjunction with

JPCA program.

 

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High Yield Rate Manufacturing Technology for EDS/EPS

Mr. Bruce Su, VP, ASE Group

 

Embedded die substrate (EDS) and embedded passive substrate (EPS) technology have been developed for many years and several manufacturing methodologies have been introduced and promoted by experts in this field. For instance, the interconnection (laser via/solder joint/Cu bump) ,substrate manufacturing flow (chip first/chip last ), production format (panel /strip type) ,all are quite different . All technologies demonstrate with good capability and competitiveness, however there are very few companies can do high volume production till now, particularly for active die embedding .The main reason is low substrate yield rate resulting in high die loss accordingly. In fact EDS/EPS technology is not purely substrate related, it is a highly integration technology of substrate / wafer bumping /package /test /SMT field etc.. ASE is well positioned to deal with this business being a substrate manufacturer as well as the largest assembly subcon.
ASE has developed an unique substrate process for EDS/EPS substrates based on prepreg dielectrics to minimize substrate warpage and has built a number of demonstrators of varying complexity, adopted pre-fabricated known good substrate (KGS) to minimize KGD loss, similar to “chip last “promoted by the others, and strip format production tool, similar to assembly / bumping line to minimize substrate low yield rate impact. Here, the substrate manufacturing process will be outlined and examples of successful demonstrators will be shown including design rules. Lastly, the other advanced structures and manufacturing concept will be introduced as well.



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Advanced Materials for Embedded Substrate

Mr. Makoto Kato, Senior Researcher, Hitachi Chemical Co., Ltd.

 

Currently various materials are proposed for PKG Substrate.

Also, we have many kinds of materials for PKG Substrates. Especially in the higher density board such as embedded substrate, various properties are needed, for example high thermal conductivity, low CTE, high density technique, and so on. Therefore I would like to introduce materials related with embedded board from our products this time.

 

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