SiP Global Summit 2018 – Day 2

Grande Luxe Banquet Friday, September 07
8:30am to 4:20pm

Date: Friday, September. 07, 2018
Venue:Grand Ballroom, Grande Luxe Banquet, 3F, CTBC Financial Park, Nangang, Taipei 
Theme:Future Package and Test for Smart Integration
Forum Chairman: 
• Dr. Yu-Po Wang/ 王愉博, Sr. Director, SPIL
• Dr. Cheng-Wen Wu/ 吳誠文, Distinguished Chair Professor, NTHU


AIOT, 5G and Networking will make our live better, and that all need small form factor, high density of system package and high performance computing packaging technologies! 

In this session, Discovered Heterogeneous Integration Roadmap(HIR), Package Industries Status and Future Trend, GPU Computing for Semiconductor Design and Manufacturing, chip with TSV Market and Technology Outlook, and it will also include positioning of the TSV solutions.The heterogeneous integration to systems in package (SiPs) is driven by various applications, and this session will show different integration approaches for both thermal bonding and hybrid bonding. Another key is Test and Diagnosis for System Level Package, Fine Pitch Memory, Automotive, ADAS and High Density Fan-Out technologies!

■ Session Focus:

● Future Market and Heterogeneous Integration Trend!

● Advanced Packaging Technologies 2.5D & 3D IC, Fan-Out Solutions, MCM Stacking and SiP for AIOT, Automotive and HPC Applications.

● Test and Diagnosis for High Density Siliconand High Density System Integration with Service Model Migration.

Early-Bird Regular
NTD 4,800 NTD 6,000

*Tax Included

*Forum agenda is subject to change

Sponsored by:


Do you want to attend this session? REGISTER NOW!

Mr. Tom Salmon
Vice President, Collaborative Technology Platforms / Executive Director, FOA
Dr. Yu-Po Wang/ 王愉博
Sr. Director
Mr. Chee Ping Lee
Technologist and Technical Marketing Senior Manager
Lam Research
Dr. Li-C. Wang
Director of Computer Engineering and Professor of Electrical and Computer Engineering
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