Mr. Markus Wimplinger 



Mr. Markus Wimplinger 


Corporate Technology Dev. & IP Director


EV Group


  • Electrical Engineering from HTL Braunau, Austria



  • Corporate Tech. Dev. & IP Director (06 – present), EV Group

  • Director Technology North America (03 – 06)

  • EV Group

  • Project Manager (01-03), EV Group

  • Multiple patent applications pending

  • Author of several papers




Markus Wimplinger is the Corporate Technology Development and IP Director at EVG. In this role, Markus oversees EV Group’s global Process Engineering team. His further responsibilities include the management of R&D partnerships and contracts with 3rd party organizations such as companies or government related entities, as well as Intellectual Property affairs associated with EVG’s process technology development efforts.


Markus received his educational background in Electrical Engineering from HTL Braunau, Austria. He started with EV Group as a project manager at the company’s headquarters in Austria in 2001 with focus on customer projects.

In 2002, Mr. Wimplinger transitioned to EV Group North America in Tempe, Arizona, USA, where he served as the Director Technology North America till August 2006. Mr. Wimplinger’s past work includes involvement in design, development, process technology and many other aspects of capital equipment production at both EV Group and at his former job with a capital equipment supplier for non-semiconductor related industries.


 Speech Abstract:

 Rethinking Chip Stacking in High Volume from Chip to Wafer, Via Last to Wafer Level Hybrid Bonding


As Moore’s law for scaling of transistor gate length is running out of steam, integration needs to be increased differently. Monolithic integration is one solution, where lithographic scaling is replaced by integration in vertical direction. Stacking and electrically contacting several semiconductor layers is challenging, as multiple unit processes have to be solved and put together. One of the key processes is aligned wafer-to-wafer bonding. Besides optimization of the alignment accuracy, particle cleaning or plasma activation, earlier upstream processing steps have important influence to a high yield hybrid bonding.

In fusion bonding, both wafers are aligned and a pre-bond is initiated. When bringing the device wafers together, wafer stress and/or bow can influence the formation of a bond wave. The bond wave describes the front where hydrogen bridge bonds are formed to pre-bond the wafers. Controlling the continuous wave formation and controlling influencing parameters is key to achieving the tight alignment specifications noted above. In essence, optimizing a fusion bonding process means that one must optimize the force generated during the bonding. Any wafer strain manifests in distortion of the wafer, which leads to an additional alignment shift. Process and tool optimization can minimize strain and significantly reduce local stress patterns. Typically, distortion values in production are well below 50nm. Indeed, further optimization of distortion values is a combination of many factors, including not only the bonding process and equipment, but also previous manufacturing steps and the pattern design.

In this contribution, we will present a study on the influencing factors for highest alignment accuracy needed for hybrid bonding. Overlay alignment accuracy of 150nm (3σ) for each point of a 300mm device wafer, which is to our knowledge industry leading results at this time, will be used as a baseline for discussion. Preprocessing and plasma activation is determining to a large extent the distortion of both product wafers and influencing factors will be discussed. Especially for hybrid copper silicon oxide interfaces, compensation of scaling effects are discussed and compensation is discussed with respect to pre-bond plasma activation and thermal compensation. Learnings of these results are discussed with respect to industry applications such as back side illuminated image sensors, where hybrid bonding is currently moving into production. Furthermore, prospective future device applications for memory stacking as well as memory on logic and their respective requirements will be shown, where hybrid bonding will be an enabling process step.



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