侯上勇 / Dr. Shang Y. Hou



侯上勇 / Dr. Shang Y. Hou


Deputy Director


3DIC Division, R&D, TSMC


  • Ph.D. Materials Science & Engineering, Stony Brook University, USA



  • Department manager,Far Backend Program, TSMC

  • Manger, Logic Technology Development, WSMC




Shang Y. Hou is currently Deputy Director of TSV Integration Program at TSMC. In the past 16 years with TSMC, he has developed a wide spectrum of expertise in backend technology. The topics includes: advanced Cu low-k interconnects, wire bond circuit under pad, lead-free packaging, chip-package interaction, and TSV based interposer integration by CoWoS®.

Prior to joining TSMC, he has worked as Section Manager in the R&D of Worldwide Semiconductor Manufacturing Co., and a post doctoral fellow in Bell Labs, New Jersey.

Hou holds M.S. and Ph.D. degrees in Materials Science from SUNY Stony Brook, and B.S. from National Cheng Kung University, Taiwan. He is author and co-author of more than 35 patents, and more than 30 papers in technical journals and conferences.


 Speech Abstract:

 Keynote Speech-1: Interposer Technology: Past, Now and Future

TSV based interposer technology found a niche in multi-chip integration in recent years. It started out from homogeneous integration with chips of the same logic functions, then evolved to heterogeneous integration with chip of different logic functions. In the most recent advances, high bandwidth memory (HBM) became available for interposer integration.  A total of 150B transistors have been demonstrated of an interposer product with SoC and HBM’s to deliver unprecedented processing power. In the next decade, interposer technology will continue to assume its important role in various FPGA, cloud, and supercomputing systems that demand highest possible performance. The Si interposer will remain as a favorable platform in the high-end application space where extremely large chip area, fine-pitch interconnect, very high pin count, and good thermal dissipation are among the top considerations.


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