+886.3.560.1777

Chinese

野中敏央 / Dr. Toshihisa Nonaka

 

 

野中敏央 / Dr. Toshihisa Nonaka

 

Technical Director

 

Packaging Solution Center, R&D eadquarters, Hitachi Chemical

 Education:

 

  • 1986 BS       The University of Tokyo

  • 1995 Ph.D.   Nagoya University  

 

 Experiences:

 

  • Leading of Advanced Package Assembly  Process development

         - Fan out, 2.1D, 3D and etc. –

        Hitachi Chemical Co., Ltd.,

  •  Leading of Material Research for  Packaging, Toray Industries, Inc. 

 

 Biography:

 

T. Nonaka is now leading advanced packaging process technology development based on materials at Packaging Solution Center of Hitachi Chemical, which covers the packages of 2.1 to 3D, FO-WLP/PLP, memory and etc. in addition to precise  evaluation of various assembly materials from MCL to EMC. He has been working on the research of the material and proces related to electronics for more than 30 years. After finishing the first half of his research carrier regarding oxide superconductor, organic super lattice, phase change optical recording material and so on, he has started to develop electronics packaging materials and processes. Those were optical wiring material, NCF, photosensitive dielectric film, high thermal conductive adhesive film, high throughput TCB process and etc.  He is now focusing on the material integration for advanced package. He has published a lot regarding packaging material and process including 3D, which had been journal articles, patents and book chapters.

He is the chairman of the System Integration Technology Committee of The Japan Institute of Electronics Packaging and a member of the technical committee of International Conference on Electronics Packaging.

 

 Speech Abstract:

 Material Based Challenge and Study of 2.1, 2.5 and 3D Integration

Enhancement of performance and miniaturization of electronic devices is pushing the multi die integration. 3D-TSV technology has been already gotten into the market of DRAM die stack like HBM and 3DS. On the other hand the integrations of including high performance logic die is mainly perusing side by side configuration, which are 2.1 and 2.5D, and FO-WLP. Two of the key technologies of them are the micro bump interconnection and the fine line fabrication.  Cost conscious is demanded for the technologies from the view point of the market expand.  Regarding 3D-TSV die stack, through put is one of major concern.  Fine line fabricated organic substrate is expected in the side by side high density interconnection. In this presentation both of them are explored based on the material. High through put multi die assembly in plane and vertical are studied with the new material. The preparation of L/S = 2 mm/2 mm wiring on the organic substrate with the new build up material and the reliability evaluation results of such a high density wiring will be reported.

 

 

Share page with AddThis