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藍章益 / Mr. Albert Lan

   

藍章益 / Mr. Albert Lan

Packaging TD

Applied Materials 

 Education:

  • Master of industrial & mechanical engineering department, Univ. of Wisconsin, Madison, USA

 Experiences:

  • Over 25 years of job experience in semiconductor industry, especially focusing on advanced packaging technologies.

  • Senior Engineering Center Director, 13 years, SPIL, which is top 3 biggest assembly house in the world.

  • PD, Quality, & Sales, 5 years, Amkor Taiwan(Bumping)

  • Vice Chairman of SEMI Taiwan PKG&TEST Committee.

  • Chairman of TILA (Taiwan Intelligent Leader Association).

  • Published more than 30 technical papers and granted more than 15 issued worldwide Patents.

 Biography:

  • Albert Lan obtained his master degree from Industrial & Mechanical Engineering department, Univ. of Wisconsin, Madison, USA.

  • Over 25 years of job experience in semiconductor industry, especially focusing on advanced packaging technologies, such as bumping, Flip Chip, Fan Out, and 2.5D.

  • He ever was Senior Engineering Center Director in SPIL for 13 years, which is top 3 biggest packaging house in the world.

  • He also ever taking care of bumping PD, and Quality jobs in Amkor Taiwan for 5 years.

  • Now he is Vice Chairman of SEMI Taiwan PKG&TEST Committee and Chairman of TILA (Taiwan Intelligent Leader Association).

  • He has published more than 30 technical papers and granted more than 15 issued worldwide Patents.

 Abstract:
 

Continual drive for growth and differentiation has created the inflection with the need for better and more efficient system integration. Advanced packaging for System Integration (SI) is being considered as a viable path towards this end due to the versatility it offers as compared to System-on-Chip (SoC). Heterogeneous integration with 2.5D-interposer has primarily been used for high end (large packages) applications. Fan-Out wafer-level packaging (FOWLP) on the other hand, is a more cost effective and versatile packaging scheme to realize packaged SI.  By the way, the recent growth in FOWLP & 2.5D/3D are driven by high-performance applications that require multi-die packaging.  As adoption of packaged SI increases, more technical challenges are expected and improvements in Cost of ownership (CoO) and yield will also be required.  To address these cost and technical challenges Applied Materials has released products for PVD, Plating, Wet cleans, Dry ETCH, CVD, and CMP that offer the highest throughput and best of class on wafer performance. Applied Materials has in parallel expanded our integrated Fan-out & 2.5D/3D development capabilities to identify high value problems enabling our products with solutions to reduce development cycle time of our customers.

 
 

 

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