孫元成 / Dr. Jack Sun



孫元成 / Dr. Jack Sun


VP of Corporate Research and CTO




  • Ph.D., Electrical Engineering, University of Illinois, USA


  • Vice President, Research and Development, TSMC
  • Senior Director, Logic Technology Development Division, TSMC



  • Dr. Jack Yuan-Chen Sun received BSEE degree from National Taiwan University and MS and Ph.D. from the University of Illinois.  He held research and management positions at IBM T.J. Watson Research Center between 1983 and 1997.  He joined TSMC R&D in 1997 as Director of Advanced Module Technology, and then Senior Director of Logic Technology.  He became Vice President of R&D in 2006, and Chief Technology Officer at TSMC in 2009.  He is currently Vice President of Corporate Research and CTO of TSMC.

  • He made key contributions to the successful energy efficient CMOS logic SOC platforms with highest routed gate density and computation throughput for the foundry/fabless industry at TSMC.  He advocated a holistic energy efficient 3Dx3D system scaling concept.  Throughout his career, he and his co-workers pioneered and set many world records in CMOS, bipolar, and BiCMOS.

  • Dr. Sun received a number of technical and management awards from IBM, TSMC, professional societies, and government.  He was awarded a TSMC Medal of Honor in 2011. He is an IEEE Fellow for his contributions to CMOS technology.  He received the IEEE EDS J.J. Ebers Award recognition in 2015.  He has authored and co-authored over 200 papers and conference presentations, 12 US patents, and several ROC patents.




  • The advances in energy-efficient Si-wafer based 3Dx3D system scaling with 3D Moore’s Law and 3D heterogeneous sub-system integration are enabling and enhancing important applications such as machine learning, autonomous driving, mobile computing, intelligent IoT, and HPC. The transistor count of latest SoC chips with 3D FinFET is already more than 20 billion, while the aggregate transistor count of a heterogeneous 3Dx3D system “super chip” is more than 150 billion when an SOC chip is combined with HBMs by CoWoS for high bandwidth/throughput HPC and machine learning. Cost-effective wafer-level 3D InFO technology is also boosting edge/mobile computing as well as HPC and future IoT. 3Dx3D superchips may have total transistor count matching the equivalent transistor number of a human brain in less than 10 years. Major government and academia research initiatives have been started on materials, processes, devices, emerging memories, chip designs, and system architectures for future application systems. There are also many challenges and opportunities in manufacturing science and equipment technologies for intelligent manufacturing of nanometer 3Dx3D systems.




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