Mr. Ankush Oberai



Mr. Ankush Oberai

Group Director, R&D

Silicon Engineering Group

Synopsys Inc.


  • MSEE



  • Synopsys: Group Director, SEG

  • Magma DA: General Manager: Knights product Division

    Patents granted for:

    Failure analysis using design rules 

    Automated inline defect characterization 

    Signal tracing through boards and chips 

    Chip cross-section identification and rendering during failure analysis 

    Failure analysis and inline defect characterization

    Virtual layer generation during failure analysis




  • The work presented here is related to faster fault localization of the systematic yield limiters and reporting them back for design or process improvements to increase the overall yield. The focus is on utilization of Failure Analysis technique for fault localization based on the results of Emission Microscope (EMMI) which reports emission hotspots marking the faulty devices in the circuit. The method explained uses computer aided design (CAD) Navigation tools in combination with images from Emission Microscope (EMMI) to improve the accuracy and efficiency of Failure Analysis. The paper presents the flow to quickly identify the failing device by correlating the photon emission spots from microscope image on the design data. EMMI is used extensively for detecting leakage current resulting from device defects, e.g., gate oxide defects/ leakage, latch-up, electrostatic discharge (ESD) failure, junction leakage, etc. This emitted light is captured as hotspots on the image. One physical defect could lead to emissions in multiple transistor. The failure analysis (FA) engineer is more interested to find that one real spot which leads to the other multiple spots. In this paper we try to show the interconnectivity of all the devices beneath those emission spots and help users to analyze the root cause in the circuit schematics. The connectivity between the devices could be direct connections through nets or indirect through “transmission gates”. The circuit schematics from the layout helps the FA engineer to focus the FA work on critical devices such as a driver and enables faster and more accurate fault localization. Existing methods to localize the defects by finding a common net connecting different hotspots is not sufficient as one physical defects could result in multiple emission spots connected to different devices. The work in the paper shows the identification of critical path passing through multiple devices and their connectivity.





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