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蔡明蒔 / Dr. Ming-Shih Tsai

 

 

蔡明蒔 / Dr. Ming-Shih Tsai

Senior Scientist

Versum Materials

 Education:

  • Ph.D. in Chemistry, National Taiwan University, R.O.C.

 Experiences:

 

  • Senior Scientist, Versum Materials Technology LLC., Taiwan Branch, responsible for developing CMP slurries for advanced semiconductor applications. (2015-present)

  • Senior Research Scientist, Cabot Microelectronic Corp., responsible for developing CMP slurries for advanced semiconductor applications. (2006-2014)

  • Research Scientist, National Nano Device Lab., responsible for BEOL interconnect application for Semiconductor manufacturing such as Chemical Mechanical Polishing, Low-k dielectric, wet cleaning processes. (1995-2006)

  • Over 50 technical papers publication in journals and con ferences

  • Over 20 US and invention patents

 

 Abstract:

 

  • For <10nm logic applications, for small line width and via feature applications, cobalt has lower resistivity and better EM performance than copper.  In general, cobalt interconnects do not require additional capping layers and barriers for reducing EM.  From line resistivity perspective, copper - cobalt crossover at 14nm if Cu liner/barrier does not scale adequately [1].  Thick Cu barrier and area continue to increase Cu resistivity creating challenges for achieving low via and line resistance.  All the above make cobalt suitable for <10nm logic interconnect applications.

  • Incorporating cobalt for <10nm logic interconnect does encounter new challenges especially for wet processes like CMP and post cleaning.  In CMP processes, issues in small feature via recess due to galvanic corrosion, adaptive selectivity for ever-changing film schemes and EOE (erosion over edge) were addressed accordingly by various approaches that may not be explicit to the industry.  All works conducted by far lead to a trend of integration by having the same or similar consumables for <10nm logic cobalt and copper interconnect CMP processes.

 

 

 

 

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