With the advancement of Cu pillar flip chip technology to smaller pitches and the ability to operate at high voltages, there are challenges for the production SOC probe cards to meet concurrent mechanical and electrical requirements. The requirement to achieve high Maximum Allowable Current (MAC) and probe compliance along with low self-inductance becomes increasingly challenging with single probe design for flip chip application. As an example, shorter probe can offer high MAC and low self-inductance with a small deflection range, compared to a longer probe that can sustain higher deflection at the expense of low MAC and high inductance. In order to balance the above tradeoff dual probe design becomes inevitable. FormFactor and Qualcomm verified a Hybrid MEMS probe card solution to meet and exceed the above requirements. Hybrid probe designs allow use of different probes for fine pitch IO area, and for larger pitch power/ ground area. FormFactor’s proprietary MEMS probe structure with composite (multi-material) probe materials provides mutually exclusive advantages for different pitches. Advantages include ~1 Amp/probe of MAC in sub‐100 μm array configuration and allowing independent optimization by maintaining MAC performance and I/O performance simultaneously. At fine pitches, the lower inductance specification can be achieved with a smaller cross-section probe but with MAC tradeoff. Similarly for larger pitches, larger cross-section probes can attain high MAC with the higher inductance. In addition to balancing the mechanical and electrical trade off, FormFactor‘s hybrid solution provides an advantage and ease for IC layout by having flexibility to accommodate small pitches and larger pitches simultaneously. In this paper, we will discuss and review the cleaning protocols for hybrid designs in production environment. Effective probe tip cleaning recipes are essential in maintaining the best current carrying capability while maintaining long product lifetime.