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Dr. John Hunt

 

 

Dr. John Hunt 

Sr. Director, Engineering

Technical Promotion

ASE

 Education:

  • M.S., Univ. of Central Florida

  • B.S., Rutgers University

 Experiences:

  • Technical support for Advanced Wafer Level and Fan Out Packaging

  • Over 40 years experience in various areas of Electronics Development & Manufacturing

  • Multiple Technical Papers, Presentations and Patents

 Abstract:

 

  • There has been tremendous growth in complex electronics functionality in our everyday lives, from the mobile electronics used in phones, tablets and computers, to ever more complex automotive electronics subsystems, including the ubiquitous and often touted Internet of Things. All of this has created the need for ever increasing density and performance in electronics packaging. 

  • Although many of the mobile applications have striven for the thinnest package possible, the increased complexity of the devices has driven the need for 3-dimensional interconnectivity. We will review how the integration of a wide variety of packaging technologies from simple Wafer Level Chip Scale to Wafer Level Fan Out, Panel Level Fan Out, Chip Last Fan Out, and 3D Fanout have ultimately led to complex Heterogenous 3D Systems in Packages. 

 

 

 

 

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