方立志 / Mr. David Fang



方立志 / Mr. David Fang


CTO, Vice President


Package Research & Development Center


Powertech Technology Inc.


  • EE graduated Chung Yuan Christian University


  • Setup and led PTI package R&D center to develop 32 chip stacking, fine pitch FC, WL and 3DIC TSV package.

  • Held multiple managerial positions in semiconductor companies of IC design, process, and packaging.

  • Has been filed and granted 50 patents worldwide.



  • SoC development is facing great challenges in recent years.  Chip split and re-constitution in a SiP could be alternative solution to expand Moore’s Law.  Fine line Fan-Out package integrated multifunction chips is a SiP to realize performance close to SoC. 

  • Panel Fan-Out utilizes both LCD and semiconductor tools which provide fine line capability as well as better production efficiency than wafer level Fan-Out’s.  Several challenges were encountered during panel level development.  The solutions would be addressed in this article.  

  • Panel Fan-Out has broad applications such as 3D SiP, PoP, PiP, embedded substrate, etc.  PTI is working with suppliers and customers to prosper the ecosystem and make Fan-Out package widely adopted in the future.




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