Dr. Dirk Rohde



Dr. Dirk Rohde

R&D Manager Electronics

Atotech Deutschland


  • PhD Chemistry


  • For the past 10 years Dirk Rohde has held various roles related to R&D at Atotech Deutschland GmbH, wherein he focused primarily on the development of innovative copper plating processes. 

  • He was the R&D Manager for Atotech's Advanced Packaging Semiconductor division for 5 years and has recently assumed the role of Global Head of R&D Electronics. 

  • Prior to Atotech, Dirk was a development engineer at Infineon and Qimonda, where he worked on materials for organic electronic devices and high-k dielectrics. 

  • Dirk received his PhD in Chemistry at Martin Luther University in Halle, Germany where he began his career as scientist for the synthesis of dyes for organic electronics. 



  • Additive impact on Cu properties for Fan-out Wafer Level Packaging applications 

  • Next generation devices for FO WLP require decreasing the RDL pitch down to 2x2µm. Redistribution layers are essential to a variety of packaging technologies, as it is with more RDLs that I/O density is increased. A higher I/O density 1) provides more physical connections to the PCB, enabling better heat flow, which is critical to thermal performance; 2) enables improved electrical performance, as more outputs results in faster electrical signals between die; 3) allows the package to perform more operations in parallel due to the presence of more electrical pathways. In sum increasing the I/O count allows for more complex, high speed die to be packaged and facilitates improved reliability performance. 

  • Successful formation and plating of such fine features, however, pose a challenge for both suppliers and manufacturers, with the primary plating challenge being the simultaneous plating of ultra fine L/S, large Cu pads, and filling of microvias with a deposition rate that optimizes throughput. Additionally, the mechanical properties and impurity requirements for the Cu deposition become more difficult to control and optimize with sub 10µm L/S: 1) large grain, polygonal Cu crystal structure for high ductility – which may influence the prevalence of cracks in the metal lines – and low resistivity which impacts electrical performance; 2) low internal stress for minimized wafer warpage and good adhesion – both of which impact yield; and 3) low organic co-deposition for minimized micro voiding. 

  • Electroplating with standard Cu electrolytes results in micro voiding that amass after thermal cycle testing and may lead to failures or breakages in the Cu metal lines. To overcome this, the bath conditions, additives, and current density should be adjusted to optimize their influence on the deposit properties in terms of impurities and grain size. This paper will discuss how additives on the molecular scale impact Cu microstructure and will present plating results achieved with a new electrolyte. 





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