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SiP Global Summit 2020 – Heterogeneous Integration NOW & FUTURE – Day 2 [Physical & On-demand]

Grand Ballroom, Grande Luxe Banquet, 3F, Building A, CTBC Financial Park Thursday, September 24
8:30am to 5:30pm

(Only those videos with speakers’permission are launched on SEMICON Taiwan 2020 Hybrid platform)

Date:Thursday, September 24th, 2020
Time:08:30 - 17:30 (08:30-09:00 for registration)
Venue:Grand Ballroom, Grand Luxe Banquet, 3F, Building A, CTBC Financial Park

Theme: Advanced 3D System Integration for Moore’s Law 2.0 & Beyond

Forum Chair:

Moderator:

Outline: 

The continuous pursuit of higher compute power with insatiable data bandwidth to meet relentless system demands from cloud computing, datacenters, enterprise servers, supercomputers, network system and edge, has urged new system integration solutions with larger footprint, denser 3D interconnect, close proximity 3D inter chip integration and new memory system. These system integration trends can effectively improve compute,data bandwidth, latency and power efficiency, which are buzzwords in system performances when benchmarking the merits of advanced system integration solutions. 

To continuously sustain the economics of scale in advanced node technology adoption, semiconductor in dustry has widely advocated the fusion of design technology co-optimization (DTCO) in IC scaling and system technology co-optimization (STCO) in system scaling. The SoC disintegration and chiplets integration through innovative heterogeneous integration technology (HIT) become important to sustain the Moore's Law by the fusion of DTCO and STCO, and advocate a path forward to a new semiconductor era. The pace of advanced chiplets integration technology accelerates not only in backend 2D/3D packaging but also in front end process of 3D chip on wafer and wafer on wafer stacking (aka SoIC). In recent years, wafer scale system integration emerges in a unique front to break through the limitation of compute power and data bandwidth offered by current mainstream packages.

In this forum, speakers from renowned academia, research institute, Design House, EDA tool, foundry, and manufacturing/materials suppliers are sharing their insights and visions. Audience would benefit from this forum to have an in depth understanding of following subjects

  • AI/5G network and HPC heterogeneous integration technology trends
  • Moore's Law 2.0 unleashed by 3D high density HIT
  • New semiconductor era advocated by innovative HIT in package form and wafer form
  • System integration challenges: 3D stacking, Large Substrate Thermal

 

 

Early-bird
(7/13-9/4)

Original
(9/5-9/25)

SEMI Member
(
7/13-9/25)
Group Registration
(
7/13-9/25)

Academia
(EMBA Excluded)
(7/13-9/25)

NTD 5,040 NTD 6,300 NTD 5,040 Extra 10% discount
(More than 5 people)
NTD 800

*Tax Included

 
 
Sponsored by:
               

 

 

 
 
* Forum agenda is subject to change

 

If SEMI should be unable to hold the exhibition/forum for any cause beyond its reasonable control, SEMI has the right to cancel the exhibit/forum with no further liability than a refund of the ticket price. SEMI shall in no event be liable for incidental or consequential damages to registrants arising from or relating to such cancellation.

For further information, please visit our website. http://www.semicontaiwan.org/en/agenda-glance

 
 
   
       

 

 

Do you want to attend this session? REGISTER NOW!

Dr. Kuo-Chung Yee
Director
Taiwan Semiconductor Manufacturing Company Limited
Dr. Shang Y. Hou
Deputy Director
Taiwan Semiconductor Manufacturing Company Limited
Dr. Chih-Hang Tung
Deputy Director
Taiwan Semiconductor Manufacturing Company Limited
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