GaN high electron mobility transistors (HEMTs) have attracted enormous attention for next-generation power switching device applications due to their superior characteristics, such as high breakdown voltage, low on-resistance, low switching loss, and high switching speed. However, those technologies also result in a severe degradation on the drive current and the on-resistance (RON). On the other hand, in order to prevent the fault turn- on effect and to simplify the circuit design, a GaN device with high Vth and wide gate voltage swing is required. Thus, there still lacks the fabrication technology to provide an E-mode GaN device with high Vth, high drive current and low RON, simultaneously. The novel technology is a hybrid ferroelectric gate dielectric stack. After the initialization process, a large number of electrons are trapped into the charge-trapping layer in the gate dielectric stack, largely increasing the gate dielectric potential barrier height to achieve a very high Vth for E-mode device. Furthermore, since this charge-trapping technology does not damage the 2DEG density, it achieves the superior device performance of a high Vth of +2.71 V, an IDS, MAX of 820 mA/mm and a low RON of 11.1Ω∙mm. Moreover, the Vth-thermal-stability and the positive bias temperature instability of the fabricated devices are also discussed in this research, and those are important issues for the power switching device applications.