Received his B.Sc. and M.Sc. In Precision Instrument Department from Tianin University in China, and his M.Sc. in Computer Science and Ph.D. in Mechanical Engineering from University of North Carolina at Charlotte USA. He worked as technology Engineering manager at Intel in the assembly and Test Development Department, mainly developing metrology and test solutions for HDI substrates and Flip Chip packaging including Embedded Bridge (EMIB) over 18 years, as Principal Engineer developing the hybrid bonding solutions over 2 years prior to joining TSMC 2023. Currently he is a director leading Advanced Packaging Metrology Engineering (APME) Division at APTS (Advanced Packaging Test Service) of TSMC, responsible for mass production of all Metrology related across Advanced Packaging Technologies covering InFo, CoWoS and SoIC etc. He held 15 patents in metrology and material areas.
