移至主內容

AI-Driven Floor Planning: Deployment in Design Flow, AI Formulation, and Measured Impact

上午 9:25 - 上午 9:50

This talk shares an industry perspective on bringing AI into real IC design workflows through AI-driven floorplanning. Rather than treating AI as a standalone demo, we focus on how to deploy it in day-to-day design flows to deliver measurable benefits: improved quality, faster turnaround, reduced manual effort, and the ability to overcome human biases and local heuristics.

 

We first introduce how the floorplanning problem can be formulated for learning-based optimization and what practical objectives and constraints matter in real projects (e.g., wirelength/PPA-related considerations and feasibility constraints). We then discuss deployment considerations—how AI fits into existing EDA steps and why combining learning-based decision making with conventional optimization is often the most effective approach. Using real design examples, we illustrate measured impact and explain what typically drives the gains, including objective/reward design and constraint handling.

 

Finally, we summarize key lessons from deployment. In particular, we highlight why unnecessary constraints can shrink the AI action space and directly limit achievable quality, and how to design constraints and post-processing (e.g., legalization) to obtain robust, feasible results. Attendees will leave with a practical roadmap for adopting AI-assisted floorplanning in industrial design teams and achieving faster, more consistent outcomes.

 

Key Technologies Covered 

  • AI-driven floorplanning deployment in a real design flow (integration points with existing EDA steps)
  • Floorplanning optimization formulation: objectives (wirelength/PPA proxies) and feasibility constraints
  • Learning-based optimization (RL-style) for floorplanning actions and iterative improvement
  • Action space & constraint design: avoiding unnecessary constraints that shrink exploration space
  • AI-learned heuristics: clustering connected blocks and leveraging aspect-ratio flexibility
  • Measured impact methodology: fair comparison vs. baseline/manual floorplans under consistent conditions
  • Wirelength/PPA-related improvements and key contributors to quality gains in practice
  • Hybrid approach: combining AI with conventional optimization for better robustness and results
  • Legalization/feasibility recovery via linear-constraint modeling and optimization (e.g., LP/convex)
  • Practical deployment cost considerations: runtime/training expectations without “LLM-scale” compute

Featured Speakers

Chia-Wei Chen

陳家偉博士

Senior Technical Manager, MediaTek Inc.

Dr. Chia-Wei Chen is a Senior Technical Manager at MediaTek’s Digital AI Technology Division. He earned his Ph.D. from the Graduate Institute of Electronics Engineering, National Taiwan University. With around 10 years of industry experience, he specializes in AI for EDA and semiconductor design automation, with an earlier background in communication algorithms.

 

His work focuses on deploying AI/ML techniques in industrial EDA flows, covering RTL/logic optimizationfloorplanning, and macro placement, to accelerate design closure and improve PPA (power, performance, and area). He has co-authored papers published at leading venues including ASSCC and DAC. Dr. Chen is passionate about bridging advanced AI methods with practical semiconductor workflows to enable next-generation silicon innovation.