Gate-All Around Process Technology: Every Monolayer Matters

10:55 am - 11:15 am

The rapid advancement of artificial intelligence is pushing the limits of CMOS device technology, which is driving the need for more advanced Logic process solutions. Area scaling has become so challenging that the FinFET transistor architecture, which has been in use since the 16nm Logic node, is transitioning to a gate-all-around (GAA) architecture at the 2nm node. The GAA layout allows for better electrostatic control of the channels as well as vertical stacking of transistors.

This abstract covers the leading-edge hardware features and processes that enable the delivery of precursors and wafer temperature control for atomic layer deposition (ALD) and single-crystal epitaxial (Epi) layer deposition of critical layers in advanced Logic technology. The continuing drive to more 3-dimensional architectures and precise layer control at the monolayer level has led to widespread adoption of ALD by the entire semiconductor industry, with rapid expansion of ALD applications currently in high-volume production. A key emerging technique – area-selective deposition (ASD) – allows films to be deposited only where needed, eliminating extra post-deposition patterning and etch steps. These ALD applications include insulators such as standard oxides, nitrides, and high-k dielectrics, as well as conductors such as metal gates and vias.

The onset of GAA devices has led to the need for Epi superlattices of silicon (Si) and silicon-germanium (SiGe) alloys of varying Ge concentrations, where atomically sharp interfaces between each Epi layer are essential in order to obtain the required final transistor performance. These more complex device geometries also necessitate lower thermal budgets while accurately controlling SiGe composition and incorporating very high concentrations of dopant atoms. The focus of this talk will be on the hardware, materials, and deposition techniques used to achieve control of these critical features at the atomic level.

Key Technologies Covered

Atomic Layer Deposition
Epitaxial Deposition
High-k Gate Dielectrics
Design-Technology Co-optimization
Gate-All-Around Technology
Area-Selective Deposition
Advanced Logic Technology

Featured Speakers

Dr. Glen Wilk

VP of Technology, ASM

Glen Wilk is a Vice President of Technology at ASM, where he currently specializes in developing novel Atomic Layer Deposition (ALD) materials and processes for advanced nodes in the semiconductor industry. Prior to his current role, Glen ran the ALD business unit for 15 years and the Epitaxy business unit for 6 years at ASM, where he was responsible for leading the development of the Pulsar, Synergis, and Intrepid products. He is very passionate about innovating disruptive and differentiated hardware, processes, and materials.

Before ASM, he worked as a Senior Member of Technical Staff in the Central Research Labs at Texas Instruments, where his interests focused on silicon-based resonant tunneling diodes, novel transistor gate stacks, and advanced process integration. Glen subsequently worked as a Distinguished Member of Technical Staff in the Advanced Materials Department at Bell Laboratories in Murray Hill, N.J., where he researched high-permittivity dielectrics, metal gate stacks, and CMOS device integration, as well as indium gallium arsenide and lithium niobate materials for high-speed and optoelectronic devices, respectively.

Glen received his bachelor’s degree in Materials Science from Cornell University, and his master’s degree and PhD in Applied Physics from Harvard University. Among his publications is an invited review paper in the Journal of Applied Physics on high-permittivity gate dielectrics with over 6,000 citations, which ranks in the Top 10 cited papers in the 90-year history of the publication. In addition, he has published solicited cover review articles in Materials Research Society Bulletin and Semiconductor International. Glen currently has over 50 journal publications and holds over 60 U.S. patents.