Panel-Level Packaging Challenges and Innovations in Lithography, Inspection, and Metrology

Panel-level packaging (PLP) is rapidly emerging as a key enabler of next-generation semiconductor manufacturing, offering significant advantages in scalability, integration density, and cost efficiency. As the industry pushes toward finer nodes and more complex system architectures, PLP is not only transforming chip packaging—it is also reshaping the design of semiconductor equipment.

Scaling PLP introduces challenges in warpage control, die placement accuracy, and achieving process uniformity across large formats. The integration of glass substrates—with their superior dimensional stability, low dielectric loss, and fine-line capability—offers promising solutions, but also presents new hurdles in handling, via formation, and process integration. Overcoming these challenges requires continued innovation in materials and packaging design.

This presentation will focus on how lithography, inspection, and metrology platforms are evolving to meet the demands of PLP. We will highlight key innovations in these areas and the importance of process control in enabling more precise, reliable, and scalable PLP solutions.

Key Technologies Covered

• Panel lithography with large field stepper
• Panel inspection system with integrated 3D metrology capabilities
• Process control for panel level packaging and glass core substrate applications