Advanced Packaging for Elevating AI System Performance

1:30 pm - 1:55 pm

AI System innovation has entered a new phase — and advanced packaging is at the center of it. As AI workloads scale beyond the limits of monolithic design, performance is defined less by individual chips and more by how tightly compute, memory, and interconnect are integrated. Bandwidth, latency, and power efficiency are increasingly determined at the package level. In this keynote, Dr. CP Hung will illustrate the current evolution about system design in the AI era, presenting that next generation of high-performance computing to be defined on advances in electrical plus optical architectures and challenging heterogeneous integration beyond.

Key Technologies Covered

Advanced Packaging Trend & Evolution
Electrical and Optical Interconnect
Heterogeneous Integration for AI

Featured Speakers

Dr. C.P. Hung

Vice President, ASE Inc.

Dr. CP Hung, an IEEE Fellow, currently serves as Vice President of Corporate Research and Development at ASE, Inc. In this role, he leads the development of next-generation technologies and oversees a comprehensive portfolio of advanced solutions spanning packaging, test, and system integration across multiple ASE and USI sites.

Dr. Hung is at the forefront of advancing semiconductor packaging technologies to address the rapidly evolving demands of the AI era. His work focuses on enabling higher performance, lower latency, increased bandwidth, and enhanced power efficiency through innovative packaging architectures and integration strategies.

He holds 435 patents covering IC packaging structures, processes, substrates, and characterization technologies, and has authored more than 155 conference and journal publications.