Powering the AI Era with 3D Integration

1:45 pm - 2:05 pm

The journey of artificial intelligence began with Alan Turing’s 1950 "Imitation Game," a visionary attempt to define machine intelligence. Today, we are witnessing a paradigm shift: the evolution from Generative AI to Agentic AI and Physical AI. AI is no longer just generating data; it is reasoning, deciding, and acting within the physical world.

 

This transformation is fueled by a revolution in semiconductor technology. The demand for massive multi-modal models has made high-bandwidth, high-capacity, and energy-efficient memory the strategic backbone of the AI era. From initial data acquisition to real-time inference, the synergy between CPUs, GPUs, and next-generation storage is critical to eliminating bottlenecks and unlocking system-wide efficiency. This infrastructure is enabling a new wave of high-value services—including multi-modal reasoning engines and autonomous agents like OpenClaw and NemoClaw—that are already scaling into multi-million dollar monthly businesses.

 

In this keynote, we will explore the cutting-edge memory and storage solutions that are driving the next leap in AI performance and power optimization.

 

Key Technologies Covered 

  • zHBM
  • zHBF
  • 3D package

Featured Speakers

Jangseok Choi

Mr. Jangseok Choi

Corporate Vice President, Memory Product Planning of Samsung Electronics

Jangseok Choi, known as JS Choi, serves as Corporate Vice President at Samsung Electronics Semiconductor, heading the Memory Product Planning Team. His responsibilities include overseeing the team, developing ecosystems, and enabling current and future memory products such as DRAM, NAND, HBM, SSDs, UFS, CXL, PIM, and automotive solutions.

A seasoned expert in memory technologies, JS Choi has led advancements in open standards through collaborations with organizations like JEDEC. As Chair of the DRAM Committee and leader of task groups for DDR3, DDR4, DDR5, and WideIO, he also co-founded Gen-Z and chaired the Open Memory Interface Working Group under the Open Power Foundation. For his contributions, he earned the JEDEC Technical Recognition Award in 2009 for establishing the DDR3 standard and the Outstanding Leadership Award in 2014 for guiding the DDR4 development process.

Over 25 years at Samsung, JS Choi has driven product and technology enablement for memory innovations, including DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5/LPDDR5X, CXL, and HBM. Previously, he specialized in high-speed memory design, focusing on Rambus DRAM, before transitioning to the product planning team to shape future DRAM solutions and expand their market reach.